Feasibility of the Microcomputers for the ADDASAT Capsule

2016 ◽  
Vol 841 ◽  
pp. 309-314
Author(s):  
Dragos Ronald Rugescu

One of the most challenging problems in developing the astrionics of the recoverable orbital ADDAHORSE microcapsule is represented by the power and size constraints which require an extreme degree of miniaturization. The size, mass and power requirements of the electronic and computing (astrionics) on-board control and command equipment can be conveniently reduced by designing an Application Specific Integrated Circuit (ASIC) which integrates sensors, autopilot logic, drivers, RF communication and interface subsystems in a single, combined SoC (System-on-Chip). The feasibility of such a device is discussed here within the bounds of the ADDAHORSE project which was proposed for structural funding in Romania in 2014. This study was conducted by the Center for Innovation and Development in the Exploration of Space (CIDES) in the emerging Făgăraș facility of the future Făgăraș Space Center in Romania.

2017 ◽  
Vol 02 (04) ◽  
pp. 1750005
Author(s):  
Oscar Alonso ◽  
Angel Diéguez ◽  
Sebastian Schostek ◽  
Marc O. Schurr

This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14[Formula: see text]mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5[Formula: see text]mW.


2018 ◽  
Vol 7 (2.23) ◽  
pp. 464
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Shubhajit Pal

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.  


Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1343
Author(s):  
Hyunjun Kim ◽  
Kyungho Kim ◽  
Hyeokdong Kwon ◽  
Hwajeong Seo

Application-Specific Integrated Circuit (ASIC)-resistant Proof-of-Work (PoW) is widely adopted in modern cryptocurrency. The operation of ASIC-resistant PoW on ASIC is designed to be inefficient due to its special features. In this paper, we firstly introduce a novel ASIC-resistant PoW for low-end microcontrollers. We utilized the measured power trace during the cryptographic function on certain input values. Afterward, the post-processing routine was performed on the power trace to remove the noise. The refined power trace is always constant information depending on input values. By performing the hash function with the power trace, the final output was obtained. This framework only works on microcontrollers and the power trace depends on certain input values, which is not predictable and computed by ASIC.


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