Design and Implementation of an Encryption/Decryption System Based on FPGA

2014 ◽  
Vol 1022 ◽  
pp. 368-371
Author(s):  
Xiao Cong Ma ◽  
Guang Hui Cai ◽  
Hong Chao Sun ◽  
Hong Ye Li
Keyword(s):  
Data Security ◽  
Ip Core ◽  
Nios Ii ◽  
Design And Implementation ◽  
Aes Algorithm ◽  
Interface Specification ◽  
Encryption And Decryption ◽  
Encryption Decryption

This paper designs an encryption and decryption system based on the FPGA. The system uses AES algorithm to encrypt and decrypt data. A pipeline IP core is designed with the reconfigurable technology complying with the Avalon bus interface specification. The IP core is applied to be a custom component on Nios II architecture so that the encryption and decryption processes through hardware can be controlled by software. Finally, the program is downloaded to the Altera DE2 development board and completes the testing of encryption and decryption processes. The system can be widely implemented in the field of data security.

Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC

2013 ◽  
Vol 347-350 ◽  
pp. 2979-2982
Author(s):  
Qing Fang Zhou ◽  
Qian Huang ◽  
Ying Yuan ◽  
Jun Yang
Keyword(s):  
Hardware Description Language ◽  
Ip Core ◽  
Verilog Hdl ◽  
Description Language ◽  
Nios Ii ◽  
Design And Implementation ◽  
Network Controller ◽  
Encryption And Decryption ◽  
Hardware Description ◽  
Encryption Decryption

The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of informationsecurity.

Design and Implementation of the Block Cipher-SMS4 IP Core

2010 ◽  
Vol 129-131 ◽  
pp. 881-885
Author(s):  
Bin Wang ◽  
Ju Long Lan ◽  
Yun Fei Guo ◽  
Yuan Yang Zhang
Keyword(s):  
Small Area ◽  
Essential Role ◽  
Block Cipher ◽  
Data Path ◽  
Ip Core ◽  
Design And Implementation ◽  
Restrained Condition ◽  
Encryption Decryption ◽  
Code Book ◽  
Block Chaining

Block ciphers play an essential role in securing the wireless communications. In this paper, an FPGA implementation of the new block cipher SMS4 is presented. The SMS4 Intellectual Property (IP) core includes a non-pipelined encryption/decryption data path with an on-the-fly key scheduler and supports both the Electronic Code Book (ECB) and Cipher Block Chaining (CBC) operation modes. Our result shows that the SMS4 IP core can achieve a high throughput using only a relatively small area. It is well suitable for the field of area restrained condition.

scholarly journals DES encryption and decryption algorithm implementation based on FPGA

2020 ◽  
Vol 18 (2) ◽  
pp. 774
Author(s):  
Subhi R. M. Zeebaree
Keyword(s):  
Data Security ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
The Internet ◽  
Clock Frequency ◽  
Hardware Implementations ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Algorithm Implementation

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

32-bit Datapath AES IP Core Based on FPGA

2013 ◽  
Vol 336-338 ◽  
pp. 1848-1851
Author(s):  
Hong Wei Tang
Keyword(s):  
Finite State Machine ◽  
State Machine ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Ip Core ◽  
Encryption And Decryption ◽  
Finite State ◽  
Encryption Decryption ◽  
Maximum Clock Frequency

This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.

scholarly journals Implementation of AES for Encryption in Vertex- 3 of FPGA Environment for Security

2019 ◽  
Vol 9 (2) ◽  
pp. 4954-4958
Keyword(s):  
Data Transmission ◽  
Data Security ◽  
Architectural Design ◽  
Advanced Encryption Standard ◽  
Main Concept ◽  
Output Data ◽  
High Data ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Data Output

Data transmission with protection is main concept which is getting demand now a days for which number of encryption of data techniques are developed and now in this paper Advanced Encryption Standard (AES) Algorithm is used and is implemented on FPGA kit using vertex-3 family. We use 128 bits consists of input, key data, output data for this design. It is called an iterative looping with replacement box, key, loop in this design for both encryption and decryption of data. We use Xilinx software platform for simulation of our design that is AES by which area utilization and throughput is increased for achieving low power consumption, high data security, reduced latency and easy architectural design. This data operation is applicable in many areas.

scholarly journals Purwarupa Perangkat Keras untuk Eksekusi Algoritma AES Berbasis FPGA

2015 ◽  
Vol 5 (2) ◽  
pp. 211
Author(s):  
Nia Gella Augoestien ◽  
Agfianto Eko Putra
Keyword(s):  
Data Security ◽  
Resource Sharing ◽  
Limited Resource ◽  
Research Use ◽  
Pipeline Architecture ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
System Data ◽  
Hardware Efficiency

AbstrakAlgoritma kriptografi AES merupakan algoritma yang sering digunakan dalam menjaga kerahasiaan data. Kerahasiaan data merupakan parameter utama pengamanan data di berbagai sistem. Keamanan data dapat dicapai dengan mengkolaborasikan algoritma AES dengan algoritma kriptosistem lainnya. Oleh karena itu,perangkat keras pengeksekusi algoritma AES dengan sumber daya terbatas menjadi sangat penting. Penelitian ini mengusulkan rancang bangun purwarupaperangkat keras untuk eksekusi algorima AES yang mengutamakan pemakaian sumber daya optimalmenggunakan FPGA tanpa mengorbankan kecepatan eksekusi. Pengoptimalan sumber daya ditempuh dengan merancang perangkat keras untuk enkripsi dengan dekripsi yang saling berbagi sumber daya, menggunakan arsitektur iteratif pada level putaran, arsitektur pipeline pada level transformasi, dan lebar data 32 bit.Purwarupa perangkat keras pada penelitian ini menggunakan FPGA Xilinx Spartan®-6 Seri (XC6LX16-CS324) hasil pemodelan telah berhasil melakukan proses enkripsi dan dekripsi. Efisiensi perangkat keras yang dicapai adalah 1,94Mbps/Slice, sedangkan lewatan yang diperoleh adalah 308,96Mbps. Dengan pemakaian sumber daya hanya 6% dari yang tersedia pada FPGA.  Kata kunci—Algoritma AES, FPGA, resource sharing, iteratif, pipeline  Abstract AES cryptography algorithm is a tool which often using to protect confidentiality of data.Confidentiality of data is principle parameter of data security in various system. Data security achieve by collaborated AES algorithm with another cryptosystem tools. Therefore, limited resource hardware to excecuteAES algorithm is very important.            This research proposed hardware prototype for excecuting AES algorithm based on FPGA. Optimumresource utilizing become basic priority in this design. So that, we are using resource sharing between hardware for encryption and decryption, iteratif architecture on round level, pipeline architecture on transformation level with 32-bit architecture at design to attain optimum resource utilizing.            Hardware prototype in this research use FPGA Xilinx Spartan®-6 (XC6LX16-CS324), encryption and decryption have been done in this hardware prototype. This prototype have 1,94Mbps/Slice hardware efficiency, 308,96Mbps throughput with only using 6% resource that available on this FPGA. Keywords— AES Algorithm, FPGA, resource sharing, iterative, pipeline

RTL Modelling for the Cipher Blcok Chaining Mode (Cbc) for Data Security

2017 ◽  
Vol 8 (3) ◽  
pp. 709
Author(s):  
Meenakshi R. K ◽  
A. Arivazhagan
Keyword(s):  
Data Transmission ◽  
Data Security ◽  
Satellite Communication ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Cryptographic Algorithms ◽  
Efficient Data ◽  
Minimum Numbers ◽  
Secured Data

<p>The demand of satellite communication, the security algorithms are to be designed in the board. The information from the satellite to the ground is required the data security with the cryptographic algorithms. Advanced encryption standard (AES) is one of the promising cryptographic algorithms for the terrestrial communication. In this paper, the encryption and decryption is mainly focused on the cipher block chaining (CBC) mode for achieving the high secured data transmission. For efficient data transmission, the AES algorithm is implemented by using CBC mode. The proposed work is designed by using RTL modeling and also the minimum numbers of logical elements are used for implementation. </p>

Performance Evaluation of Selected Encryption Algorithms

2021 ◽  
Vol 10 (2) ◽  
pp. 21-30
Author(s):  
Ahmida ABIODUN ◽  
Olanrewaju LAWAL ◽  
Oyediran OYEBIYI ◽  
Odiete JOSEPH ◽  
Adeyemi ADETORO
Keyword(s):  
Data Security ◽  
Hybrid Algorithm ◽  
Process Time ◽  
Advanced Encryption Standard ◽  
Algorithm Performance ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Sequential Combination ◽  
Encryption Algorithms ◽  
Exclusive Or

Data security is a key aspect of today’s communication trend and growth. Various mechanisms have been developed to achieve this security. One is cryptography, which represents a most effective method of enhancing security and confidentiality of data. In this work, a hybrid based 136bit key algorithm involving a sequential combination of XOR (Exclusive –Or) encryption and AES (Advanced Encryption Standard) algorithm to enhance the security strength is developed. The hybrid algorithm performance is matched with XOR encryption and AES algorithm using encryption and decryption time, throughput of encryption, space complexity and CPU process time.

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