Design of a High-Speed Digital FIR Filter Based on FPGA

2012 ◽  
Vol 433-440 ◽  
pp. 4571-4577
Author(s):  
Guo Sheng Xu
Keyword(s):  
Digital Filter ◽  
High Speed ◽  
Input Data ◽  
Finite State Machine ◽  
Hardware Implementation ◽  
Simple Structure ◽  
Design Method ◽  
Fir Filter ◽  
Finite State ◽  
Linear And Nonlinear

To realize filtering of high-speed input data, and aiming at the design method of systolic FIR digital filter, this paper proposes a design method of high-speed FIR filter based on FPGA. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated, it can reduce the input dimension and eliminate linear and nonlinear interference effectively. In addition, it is very suitable for hardware implementation due to its simple structure.

Design of Reconfigurable FIR Filter System Based on FPGA

2012 ◽  
Vol 433-440 ◽  
pp. 4669-4674
Author(s):  
Guo Sheng Xu
Keyword(s):  
Real Time ◽  
Digital Filter ◽  
Finite State Machine ◽  
Fir Filter ◽  
State Machine ◽  
Experimental Results ◽  
The Real ◽  
Filter System ◽  
Finite State ◽  
Fir Digital Filter

In order to improve the real-time and flexible of FIR digital filter, a reconfigurable FIR filter system based on FPGA is designed. According to the filter specialties, the filter coefficients are calculated by the computer. And the configured coefficients of the multistage FIR filter are downloaded to the chip. The filtering computing is completed by the FPGA. The filtered data is transmitted to the computer through the USB2.0 interface for further processing, such as displaying, analyzing and storing. The states conversion between coefficients configuring mode and filtering mode is finished by FSM (Finite State Machine), which ensures the system to work orderly. The experimental results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, and the filter is effective，that it can effectively filter out the noise signals.

scholarly journals RECONFIGURABLE SELF-ADDRESSABLE MEMORY-BASED FSM A SCALABLE INTRUSION DETECTION ENGINE

2012 ◽  
pp. 144-151
Author(s):  
B. SRILATHA ◽  
KRISHNA KISHORE
Keyword(s):  
High Speed ◽  
Finite State Machine ◽  
State Machine ◽  
Network Attack ◽  
Memory Efficiency ◽  
Attack Pattern ◽  
Current State ◽  
Incoming Packet ◽  
Finite State ◽  
Attack Patterns

One way to detect and thwart a network attack is to compare each incoming packet with predefined patterns, also Called an attack pattern database, and raise an alert upon detecting a match. This article presents a novel pattern-matching Engine that exploits a memory-based, programmable state machine to achieve deterministic processing rates that are Independent of packet and pattern characteristics. Our engine is a self addressable memory based finite state machine (samFsm), whose current state coding exhibits all its possible next states. Moreover, it is fully reconfigurable in that new attack Patterns can be updated easily. A methodology was developed to program the memory and logic. Specifically, we merge “non-equivalent” states by introducing “super characters” on their inputs to further enhance memory efficiency without Adding labels. This is the most high speed self addressable memory based fsm.sam-fsm is one of the most storage-Efficient machines and reduces the memory requirement by 60 times. Experimental results are presented to demonstrate the Validity of sam-fsm.

High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations

2015 ◽  
Vol 24 (07) ◽  
pp. 1550101 ◽  
Author(s):  
Raouf Senhadji-Navaro ◽  
Ignacio Garcia-Vargas
Keyword(s):  
High Speed ◽  
Finite State Machine ◽  
State Of The Art ◽  
Behavioral Model ◽  
State Machine ◽  
The State ◽  
Experimental Results ◽  
State Machines ◽  
Finite State ◽  
Area Efficient

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.

Reconfigurable finite-state machine based IP lookup engine for high-speed router

2003 ◽  
Vol 21 (4) ◽  
pp. 501-512 ◽  
Author(s):  
M. Desai ◽  
R. Gupta ◽  
A. Karandikar ◽  
K. Saxena ◽  
V. Samant
Keyword(s):  
High Speed ◽  
Finite State Machine ◽  
State Machine ◽  
Ip Lookup ◽  
Finite State

Design of Finite State Machine Based on VHDL

2012 ◽  
Vol 529 ◽  
pp. 335-338 ◽  
Author(s):  
Zhi Ping Zhu ◽  
Yong Qin Liu ◽  
Hong Sheng ◽  
Feng Ye
Keyword(s):  
Finite State Machine ◽  
Design Method ◽  
State Machine ◽  
Machine Design ◽  
General State ◽  
Encoding Scheme ◽  
Advantages And Disadvantages ◽  
Finite State

Different encoding scheme and method for process description of state machine are analyzed in detail, and the advantages and disadvantages of each are pointed out. The general state machine design method is given by a specific example program, according to the actual need, designers can choose different encoding scheme and method for process description to design.

scholarly journals A model of parallel sorting neural network of discrete-time

2020 ◽  
Vol 1 (1) ◽  
pp. 67-72
Author(s):  
P. Tymoshchuk
Keyword(s):  
Neural Network ◽  
Discrete Time ◽  
High Speed ◽  
Input Data ◽  
Hardware Implementation ◽  
Unknown Input ◽  
System Of Differential Equations ◽  
Parallel Sorting ◽  
Step Functions ◽  
Finite Resolution

A model of parallel sorting neural network of discrete-time is presented. The model is described by a system of differential equations and by step functions. The network has high speed, any finite resolution of input data and it can process unknown input data of finite values located in arbitrary finite range. The network is characterized by moderate computational complexity and complexity of hardware implementation. The results of computer simulation illustrating the efficiency of the network are provided.

scholarly journals Optimal Differential Routing based on Finite State Machine Theory

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 105-117 ◽  
Author(s):  
M. S. Krishnamoorthy ◽  
James R. Loy ◽  
John F. McDonald
Keyword(s):  
High Speed ◽  
Finite State Machine ◽  
Linear Time ◽  
State Machine ◽  
Formal Proof ◽  
Routing Problem ◽  
Differential Signal ◽  
Finite State ◽  
Machine Theory ◽  
Proof Of Correctness

Noise margins in high speed digital systems continue to erode. Full differential signal routing provides a mechanism for deferring these effects. This paper proposes a three stage routing process for solving the adjacent placement routing problem of differential signal pairs, and proves that it is optimal. The process views differential pairs as logical nets; routes the logical nets; then bifurcates the result to achieve a physical realization. Finite state machine theory provides the critical theoretical underpinning and formal proof of correctness necessary for linear time bifurcation. Regular expressions map the theoretical solution to an appropriate implementation strategy that employs feature vectors for net recognition.

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