Design of High-Order Chaotic Circuits
As an expansion and extension for three-order and four-order Chua's circuit, a new method to construct a class of high-order Chua's circuit and its FPGA hardware implementation has been studied in this paper. Based on the structure of a typical third-order Chua's circuit, a fifth-order, sixth-order and seventh-order Chua's circuit have been constructed through the series in the-type sub-circuit made up by a negative resistance, capacitance, inductance, and resistance, which are stringed into on the inductance slip. The dimensionless equation of high-order Chua's circuit has been, then, derived, and its basic dynamics characteristics have also been analyzed, among which including the phase diagram of chaotic attractors, the dynamic behavior of equilibrium points, bifurcation diagram and the Lyapnuov exponents. Due to digital processing technology, the continuous time state equation of the system has been discretizationed and the state variable ratio transformation has been done, so that the chaotic attractors of high-order Chua's circuit can be generated by using FPGA technology. Taking seventh-order Chua's circuit as a typical example, a general design principle by the way of FPGA technology to generate chaotic attractors as well as the corresponding hardware realization has been presented.