Low Thermal Budget Ohmic Contact Formation by Laser Anneal

In this work, we demonstrate the possibility to achieve an ohmic contact using a low thermal budget applicable to backside processing after wafer thinning. The process window for laser annealing as a function of the thinning process is investigated. By laser melt annealing, we demonstrate the possibility for different silicide phases from pure nickel deposition on thinned 4H-SiC, formation of uniform carbon nanoclusters at the metal/SiC interface and recovery of thinning-induced defects. This has been demonstrated as a function of different thinning process and surface conditions.

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Pulsed-Laser Annealing, a Low-Thermal-Budget Technique for Eliminating Stress Gradient in Poly-SiGe MEMS Structures

Journal of Microelectromechanical Systems ◽

10.1109/jmems.2004.832189 ◽

2004 ◽

Vol 13 (4) ◽

pp. 669-675 ◽

Cited By ~ 29

Author(s):

S. Sedky ◽

R.T. Howe ◽

T.-J. King

Keyword(s):

Laser Annealing ◽

Stress Gradient ◽

Pulsed Laser ◽

Thermal Budget ◽

Pulsed Laser Annealing ◽

Low Thermal Budget

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Investigation on the ohmic characteristic of Ni/Ti/4H-SiC

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v10i5.3174 ◽

2021 ◽

Vol 10 (5) ◽

pp. 2496-2502

Author(s):

M. I. Idris ◽

Z. A. F. M. Napiah ◽

Marzaini Rashid ◽

M. N. Shah Zainudin ◽

Siti Amaniah Mohd Chachuli ◽

...

Keyword(s):

Ohmic Contact ◽

High Vacuum ◽

Annealing Process ◽

Contact Resistivity ◽

Transmission Line Model ◽

Thermal Budget ◽

Current Voltage ◽

Vacuum Forming ◽

Effect Transistor ◽

Low Thermal Budget

Ohmic contact is important for silicon carbide (SiC) devices such as Schottky diode, junction field effect transistor (JFET) and metal oxide transistor (MOSFET). The effect of post metallization annealing (PMA) on the ohmic characteristics of Ni/Ti/4H-SiC is investigated. The samples were annealed under different ambients of high vacuum, forming gas and N2 gas at 1050˚C for 3 minutes using rapid thermal process (RTP). Current-voltage (I-V) measurements taken for different distances of a transmission line model (TLM) structure have been utilized to extract the contact resistivity. The correlation between surface roughness and resistivity has been investigated. It was found that the involvement of nitrogen during the annealing process at 1050˚C was ineffective to reduce the contact resistivity. The resistivity is improved when the samples were annealed in forming gas (FG), (a mixture of H2+N2) environment, showing that the incorporation of H2 gas during the annealing process has produced a better result. On the other hand, high vacuum PMA was found to be effective to improve the ohmic characteristic with higher current level at lower voltage. Hence, the enhanced performance observed in high vacuum annealing samples is beneficial to get ohmic contact on Ni/Ti/4H-SiC for PMA process with a low thermal budget.

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Low-thermal-budget Au-free ohmic contact to an ultrathin barrier AlGaN/GaN heterostructure utilizing a micro-patterned ohmic recess

Journal of Semiconductors ◽

10.1088/1674-4926/42/9/092801 ◽

2021 ◽

Vol 42 (9) ◽

pp. 092801

Author(s):

Wen Shi ◽

Sen Huang ◽

Xinhua Wang ◽

Qimeng Jiang ◽

Yixu Yao ◽

...

Keyword(s):

Ohmic Contact ◽

Thermal Budget ◽

Gan Heterostructure ◽

Low Thermal Budget

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Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

Applied Physics Express ◽

10.7567/apex.10.026502 ◽

2017 ◽

Vol 10 (2) ◽

pp. 026502 ◽

Cited By ~ 5

Author(s):

Wen-Hsien Huang ◽

Jia-Min Shieh ◽

Ming-Hsuan Kao ◽

Chang-Hong Shen ◽

Tzu-En Huang ◽

...

Keyword(s):

Laser Annealing ◽

Pulsed Laser ◽

Thermal Budget ◽

Pulsed Laser Annealing ◽

Low Thermal Budget

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Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Micromachines ◽

10.3390/mi11080741 ◽

2020 ◽

Vol 11 (8) ◽

pp. 741

Author(s):

Tung-Ying Hsieh ◽

Ping-Yi Hsieh ◽

Chih-Chao Yang ◽

Chang-Hong Shen ◽

Jia-Min Shieh ◽

...

Keyword(s):

Integrated Circuits ◽

Laser Annealing ◽

Three Dimensional ◽

Far Infrared ◽

Superior Performance ◽

Nanosecond Laser ◽

Thermal Budget ◽

Si Nanowire ◽

Single Grain ◽

Low Thermal Budget

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

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Silicides for 65 nm CMOS and Beyond

MRS Proceedings ◽

10.1557/proc-765-d7.5 ◽

2003 ◽

Vol 765 ◽

Cited By ~ 16

Author(s):

Jorge A. Kittl ◽

Anne Lauwers ◽

Oxana Chamirian ◽

Mark Van Dal ◽

Amal Akheyar ◽

...

Keyword(s):

Thermal Stability ◽

Sheet Resistance ◽

Kinetic Studies ◽

Process Window ◽

Thermal Budget ◽

Diffusion Limited ◽

Mechanism Of Degradation ◽

Low Thermal Budget ◽

Thermal Stability Of ◽

Ni Silicides

AbstractAn overview of silicide development for the 65 nm node and beyond is presented. The scaling behavior of Co based and Ni based silicides to sub-100 nm junctions and sub-40 nm gate lengths was investigated. Co and Co-Ni silicides required a high thermal budget to achieve low diode leakage. Even for lower thermal budgets, the sheet resistance of Co and Co-Ni silicides increased at gate lengths below 40 nm. NiSi had low sheet resistance down to 30 nm gate lengths exhibiting a reverse linewidth effect (sheet resistance decreased with decreasing linewidth), achieved lower contact resistivity than CoSi2 and lower diode leakage for similar sheet resistance values. Bridging issues cannot be ignored for NiSi, in particular for thicker Ni films, higher RTP temperatures and in the presence of Ti. Material issues for the application of NiSi were also investigated. Ni2Si was found to grow with diffusion limited kinetics in the 225-300°C range, with an activation energy of 1.5 eV. Results of the kinetic studies were used to design a two-step RTP process that limited the silicide thickness on small features by a low thermal budget first RTP step, reducing the reverse linewidth effect and avoiding excessive silicidation. In the presence of an interfacial oxide, undesired epitaxial NiSi2 pyramidal grains grew directly at temperatures as low as 310°C on p+ Si. Thermal stability of NiSi was also investigated. We found that the initial mechanism of degradation for thin NiSi films was agglomeration, with activation energies of 2.5-3 eV. The surface after agglomeration remained quite flat with alternating NiSi and exposed Si areas, while the interface roughened significantly. Thick films also degraded initially by agglomeration at low temperatures, but by transformation to NiSi2 at higher temperatures. The addition of Pt improved thermal stability of NiSi films against agglomeration. The Ni/Si-Ge reaction was also studied, finding that the addition of Ge reduced the thermal process window and resulted in a slightly higher resistivity.

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