Acceleration Factor to relate Thermal Cycles to Power Cycles for Ceramic Ball Grid Area Array Packages

2006 ◽  
Vol 3 (4) ◽  
pp. 177-193 ◽  
Author(s):  
Andy Perkins ◽  
Krishna Tunga ◽  
Suresh Sitaraman
Keyword(s):  
Fatigue Life ◽  
Environmental Parameters ◽  
Acceleration Factor ◽  
Junction Temperature ◽  
Design Parameters ◽  
Substrate Thickness ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Ceramic Ball ◽  
Wiring Board

There is a need for a new Acceleration Factor (AF) that can relate Accelerated Thermal Cycle (ATC) fatigue life to Power Cycle (PC) fatigue life quickly and accurately in order to avoid over designing electronic packages for benign environments. An AF, such as the Norris-Landzberg AF, is only applicable when using it to predict fatigue life within the same environment, i.e. ATC to ATC or PC to PC. This work proposes an AF that takes into account the differences between ATC tests and PC tests for ceramic ball grid array (CBGA) packages by considering relevant design and environmental parameters. The new AF is based on relevant design parameters such as substrate size, substrate thermal conductivity, substrate thickness, coefficient of thermal (CTE) mismatch between the substrate and printed wiring board (PWB), PWB thickness, and environmental parameters such as temperature range (ΔT), frequency of cycles (f), and peak/junction temperature (Tj). Finite Element Models (FEM), experimental data, laser moiré interferometry, Design of Simulation (DOS), ANOVA, and regression analysis are used to develop the new AF. The new AF can be used to more accurately assess PC fatigue life from ATC tests so that expensive over-designing of electronic packages can be avoided for desktop/server/laptop applications.

Extending the Fatigue Life of Solder Grid Array (SGA) Electronic Packages

2003 ◽  
Vol 125 (1) ◽  
pp. 18-23 ◽  
Author(s):  
Michael C. Larson ◽  
Melody A. Verges
Keyword(s):  
Fatigue Crack ◽  
Fatigue Life ◽  
Crack Opening ◽  
Shear Loading ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Force Mode ◽  
Wiring Board ◽  
Crack Growth Model

A fracture mechanics approach is used to investigate how the fatigue life of a solder grid array (SGA) may be increased or decreased by the application of an axial force to individual solder interconnects, such as may be induced by use of an underfill, by warping of a printed wiring board, or by some other mechanical constraint. The predominant loading on the SGA is assumed to be the shear resulting from a difference in thermal expansion between the package and the printed wiring board in the presence of cyclic temperature variations. A fatigue crack growth model, akin to the Paris law, is proposed for the cycles to failure of an individual cracked interconnect which undergoes a cyclic mode-II shear loading in conjunction with either a constant crack opening force (mode-I) or a constant crack closing force. For typical SGA packages in use today, the model predicts that forces on the order of only one newton can significantly impede or accelerate the propagation of a fatigue crack.

Effects of Ceramic Ball-Grid-Array Package’s Manufacturing Variations on Solder Joint Reliability

1994 ◽  
Vol 116 (4) ◽  
pp. 242-248 ◽  
Author(s):  
Teh-Hua Ju ◽  
Wei Lin ◽  
Y. C. Lee ◽  
Jay J. Liu
Keyword(s):  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Printed Wiring Board ◽  
Ceramic Ball ◽  
Solder Volume ◽  
Bga Package ◽  
Reliability Of Solder Joints ◽  
Wiring Board

The effects of manufacturing variations on the reliability of solder joints between a ceramic ball grid array (BGA) package and a printed wiring board (PWB) are investigated. Two cases are studied, namely, with and without spacers between the BGA package and the PWB to maintain the solder joint height. Manufacturing variations considered include changes in solder volume, joint height, and pad size. To evaluate the effect of manufacturing variations on reliability, every possible solder joint profile is first derived. The maximum strain is calculated next. Finally, the fatigue life is predicted. The calculations show that these manufacturing variations change the joint profile, and subsequently affect the fatigue life. Since the package is heavy, the use of spacers is necessary to control the solder joint height for reliable connections, and to maintain a large gap for cleaning. The solder joints formed with the use of spacers, may have convex, cylindrical or concave profiles. The concave solder joints are preferred, since they have long fatigue lives and are less sensitive to the manufacturing variations. For the convex solder joints, their fatigue lives are strongly affected by the joint height variation caused by package warpage and by the combined effects of solder volume and pad size.

Warpage Measurement Using Projection Moire´ System and Two Automatic Image Segmentation Algorithms

2007 ◽  
Author(s):  
Wei Tan ◽  
I. Charles Ume
Keyword(s):  
Image Segmentation ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Segmentation Algorithms ◽  
Out Of Plane ◽  
Cte Mismatch ◽  
Image Models ◽  
Wiring Board ◽  
Plane Displacement ◽  
Projection Moire

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to serious reliability problems. In this paper, a projection moire´ warpage measurement system and two types of automatic image segmentation algorithms were presented. In order to use the projection moire´ technique to separately determine the warpage of a PWB and assembled electronic packages in a PWBA, two image segmentation algorithms based on mask image models and active contour models (snakes) were developed. They were used to detect package locations in a PWBA displacement image generated by the projection moire´ system. The performances of the mask image and snake approaches based on their resolutions, processing rates, and measurement efficiencies were evaluated in this research. Real-time composite Hermite surface models were constructed to estimate the PWB warpage values underneath the electronic packages. The above automatic image segmentation algorithms were integrated with the projection moire´ system to accurately evaluate the warpage of PWBs and assembled chip packages individually.

Three- and Four-Point Bend Testing for Electronic Packages

2003 ◽  
Vol 125 (4) ◽  
pp. 556-561 ◽  
Author(s):  
Santosh Shetty ◽  
Tommi Reinikainen
Keyword(s):  
Bending Test ◽  
Electronic Packages ◽  
Reliability Model ◽  
Test Results ◽  
Printed Wiring Board ◽  
Reliability Models ◽  
Four Point Bending ◽  
Three Point Bend Test ◽  
Point Bend ◽  
Wiring Board

This study demonstrates the application of three-point and four-point bending tests for evaluating the reliability of chip scale packages under curvature loads. A three-point bend test is conducted on 0.5-mm-pitch chip-scale packages (CSPs) mounted on FR4 (Flame Retardant) substrates. This test is simulated by using the finite element method and the results are calibrated experimentally to formulate a reliability model. A three-point bend scheme is an ideal choice for generating reliability models because multiple packages can be tested under multiple loads in a single test. This reliability model can be used to predict the durability of the packages in the real product under any printed wiring board (PWB) curvature loading conditions. A four-point bending simulation is also demonstrated on the test substrate. Four-point bending test is an ideal method for testing a larger sample size of packages under a particular predefined stress level. This paper describes the bending simulation and testing on packages in a generic sense. Due to the confidentiality of the test results, the package constructional details, material properties, and the actual test data have not been presented here.

Design of Experiments in Ball Grid Array Thermal Fatigue Life Tests

2002 ◽  
Author(s):  
T. E. Wong ◽  
C. Y. Lau ◽  
L. A. Kachatorian ◽  
H. S. Fenger ◽  
I. C. Chen
Keyword(s):  
Fatigue Life ◽  
Thermal Fatigue ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Temperature Cycling ◽  
Design Parameters ◽  
Physical Analysis ◽  
Printed Wiring Board ◽  
Thermal Fatigue Life ◽  
The Impact

The objective of the present study is to evaluate the impact of electronic packaging design/manufacturing process parameters on the thermal fatigue life of ball grid array (BGA) solder joints. The four selected parameters are BGA under-fill materials, conformal coating, solder pad sizes on printed wiring board, and BGA rework, with each having either two or three levels of variation. A test vehicle (TV), on which various sizes of BGA daisy-chained packages are soldered, is first designed and fabricated, and then subjected to temperature cycling (−55°C to +125°C) with continuous monitoring of solder joint integrity. The total of 15 experimental cases is used in the present study. Based on monitored results, a destructive physical analysis is conducted to further isolate the failure locations and determine the failure mechanisms of the solder joints. Test results indicate that the influence of these design parameters on fatigue life is dependent on the particular package, in some instances improving the fatigue life tenfold.

Design parameters and environmental impact of printed wiring board manufacture

2019 ◽  
Vol 238 ◽  
pp. 117807 ◽  
Author(s):  
Maria Lourdes Alcaraz Ochoa ◽  
Haoyang He ◽  
Julie M. Schoenung ◽  
Erkko Helminen ◽  
Tom Okrasinski ◽  
...  
Keyword(s):  
Environmental Impact ◽  
Design Parameters ◽  
Printed Wiring Board ◽  
Wiring Board

Comparison of Warpage Measurement Capabilities and Results Obtained by Using Laser and Digital Fringe Projection Methods

2014 ◽  
Vol 136 (3) ◽  
Author(s):  
Sungbum Kang ◽  
I. Charles Ume
Keyword(s):  
Projection Methods ◽  
Fringe Projection ◽  
Electronic Packages ◽  
Printed Wiring Board ◽  
Full Field ◽  
Digital Fringe Projection ◽  
Accuracy And Precision ◽  
Wiring Board ◽  
Thermomechanical Reliability ◽  
Measurement Capabilities

Electronic packaged devices are becoming increasingly smaller in size and higher in density while requiring higher performance and superior reliability. Warpage is one of the crucial factors for the thermomechanical reliability of electronic packages and warpage control becomes a more crucial process during the printed wiring board (PWB) fabrication and package assembly processes. This requirement necessitates more accurate methods of measuring warpage. The fringe projection methods are recent trends for measuring the warpage of chip packages, PWBs, and PWB assemblies (PWBAs) because of their noncontact, full-field, and high-resolution measurement capabilities. This paper presents a comparison of two fringe projection methods: laser fringe projection (LFP) (projection moiré) and digital fringe projection (DFP). Experimental results show that digital fringe projection has higher practical resolution, and better accuracy and precision than laser fringe projection.

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