Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration

Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..

Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules

System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).

A Through-Hole Lead Connection Method for Thin-Film Thermocouples on Turbine Blades

To solve the current problems with thin-film thermocouple signals on turbine blades in ultra-high temperature environments, this study explores the use of a through-hole lead connection technology for high-temperature resistant nickel alloys. The technique includes through-hole processing, insulation layer preparation, and filling and fixing of a high-temperature resistant conductive paste. The through-hole lead connection preparation process was optimized by investigating the influence of the inner diameter of the through-hole, solder volume, and temperature treatment on the contact strength and surface roughness of the thin-film for contact resistance. Finally, the technology was combined with a thin-film thermocouple to perform multiple thermal cycling experiments on the surface of the turbine blade at a temperature of 1000 °C. The results show that the through-hole lead connection technology can achieve a stable output of the thin-film thermocouple signal on the turbine blade.

Design of Solder Connections for Self-Assembly of Optoelectronic Devices

In surface mount assembly, advantage is taken of the high surface tension of molten solder to self-align ball grid array packages and flip chip die. However, in these applications, the volume of solder applied as paste by stencil printing is not sufficiently well controlled to achieve the precise alignment required for optoelectronic devices. We believe that the requirement on solder volume control for assembly of optoelectronic devices can be relaxed by designing the bond pads so that the height or alignment of connections is controlled by the surface tension of the solder rather than its volume. Our design approach to accomplishing this is to connect auxiliary pads to the primary attachment pad, which act as solder reservoirs. Surface tension causes the solder to be redistributed among these pads to achieve a uniform pressure throughout the solder volume. This phenomena is governed by the Young-Laplace equation, ΔP = γκ, in which ΔP represents the difference in pressure within and outside the solder, γ the surface tension of the solder, and κ the local curvature of the solder surface. Thus, the design of the set of primary and auxiliary pads is critically important to realizing the desired control of joint height. In this article, we describe the use of the Surface Evolver software package in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume. Specifically, we calculate the equilibrium shape of the solder surface over the connected set of pads and examine how control of joint height is affected by the number, size, and geometry of auxiliary pad configurations.

Design of Solder Connections for Self-Assembly of Optoelectronic Devices

The cost of optoelectronic assemblies is significantly higher than that of electronic assemblies due in large part to the method of assembly. A typical computer circuit board is built by screen printing solder paste onto a printed wiring board, placing components on the board at rates of several thousand per hour, and then reflowing the solder paste in a conveyor oven. By contrast, optoelectronic assemblies are built up in a sequential process in which epoxy is dispensed for a single component, which is placed and held in position until the epoxy is cured. Many minutes are required to build an optoelectronic assembly, such as a laser module, by this approach, also the precision robotic placement tool needed for this process costs in excess of a million dollars. The demand for all types of optoelectronic components in communications, computing, automotive, medical and aerospace applications is great, but the high cost of manufacture is constraining growth, so clearly a better method of assembly is needed. In surface mount assembly, advantage is taken of the high surface tension of molten solder to self-align ball grid array packages and flip chip die. However, in these applications, the volume of solder applied as paste by stencil printing is not sufficiently well controlled to achieve the precise alignment required for optoelectronic devices. We believe that the requirement on solder volume control for assembly of optoelectronic devices can be relaxed by designing the bond pads so that the height or alignment of connections is controlled by surface tension of the solder rather than its volume. Our design approach to accomplishing this is to connect auxiliary pads to the primary attachment pad, which act as solder reservoirs. Surface tension causes solder to be redistributed among these pads to achieve a uniform pressure throughout the solder volume. This phenomena is governed by the Young-Laplace equation, ΔP = γκ, in which ΔP represents the difference in pressure within and outside the solder, γ the surface tension of the solder and κ the local curvature of the solder surface. Thus, the design of the set of primary and auxiliary pads is critically important to realizing the desired control of joint height. In this paper we describe the use of the Surface Evolver software package in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume. Specifically, we calculate the equilibrium shape of the solder surface over the connected set of pads and examine how control of joint height is affected by the number, size and geometry of auxiliary pad configurations. We also discuss results from some preliminary experiments that we are conducting to validate our modeling results.