Embedded System Protocol Design Flow based on SDL: From Specification to Hardware/Software Implementation

2008 ◽  
Author(s):  
Daniel Dietterle
Keyword(s):  
Embedded System ◽  
Protocol Design ◽  
Design Flow ◽  
Software Implementation

UML as Front-End Language for Embedded Systems Design

2010 ◽  
pp. 1-23
Author(s):  
Lisane Brisolara de Brisolara ◽  
Marcio Eduardo Kreutz ◽  
Luigi Carro
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Systems Design ◽  
Design Flow ◽  
Domain Specific ◽  
History Of ◽  
Uml Diagrams ◽  
The Embedded System ◽  
Definition Of

This chapter covers the use of UML as a modeling language for embedded systems design. It introduces the UML language, presenting the history of its definition, its main diagrams and characteristics. Using a case study, we show that using the standard UML with its limitations one is not able to model many important characteristics of embedded systems. For that reason, UML provides extension mechanisms that enable one to extend the language for a given domain, through the definition of profiles covering domain-specific applications. Several profiles have been proposed for the embedded systems domain, and some of those that have been standardized by OMG are presented here. A case study is also used to present MARTE, a new profile specifically proposed for the embedded system domain, enabling designers to model aspects like performance and schedulability. This chapter also presents a discussion about the effort to generate code from UML diagrams and analyses the open issues to the successful use of UML in the whole embedded system design flow.

Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system

2003 ◽  
Author(s):  
David Hwang ◽  
Bo-Cheng Lai ◽  
Patrick Schaumont ◽  
Kazuo Sakiyama ◽  
Yi Fan ◽  
...  
Keyword(s):  
Embedded System ◽  
Design Flow

Implementation of USB in Embedded Systems Based on ARM Microprocessor

2014 ◽  
Vol 596 ◽  
pp. 883-887
Author(s):  
Xin Li Li
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Hardware Design ◽  
Implementation Process ◽  
Cost Effective ◽  
Software Implementation ◽  
Application System ◽  
Arm Microprocessor ◽  
Working Principle

S3C4510B is a cost-effective 16/32 bit RISC microcontroller based on Ethernet application system, and ISP1161 is a chip which is designed to implement USB protocol in an embedded system. Here, we design and implement embedded systems USB with ISP1161 chip based on ARM microprocessor S3C4510B. This paper describes the basic working principle of ISP1161 chip and hardware design of the system, and presents the software implementation process of USB in embedded systems.

scholarly journals Software for Simplifying Embedded System Design Based on Event-Driven Method

2015 ◽  
Vol 5 (3) ◽  
pp. 491 ◽  
Author(s):  
Maman Abdurohman ◽  
Arif Sasongko
Keyword(s):  
Embedded System ◽  
System Design ◽  
Design Process ◽  
Design Flow ◽  
Market Demand ◽  
Code Generator ◽  
Embedded System Design ◽  
Event Driven ◽  
Study Test ◽  
Speed Accuracy

Complexity of embedded system application increases along with the escalation of market demand. Embedded system design process must be enhanced to face design complexity problem. One of challenges in designing embedded system is speed, accuracy, and flexibility. The design process is usually conducted recursively to fulfill requirement of user and optimization. To solve this problem, it needs a system design that is flexible for adaptation. One of solutions is by optimizing all or some of the design steps. This paper proposes a design framework with an automatic framework code generator with of event driven approach. This software is a part of a design flow which is flexible and fast. Tron game and simple calculator are presented as a case study. Test result shows that this framework generator can increase speed of design’s flexibility.

Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool

MACRo 2015 ◽  
2015 ◽  
Vol 1 (1) ◽  
pp. 183-191 ◽  
Author(s):  
Tibor Tămas ◽  
Sándor Tihamér Brassai
Keyword(s):  
Embedded System ◽  
Fuzzy Inference ◽  
Fuzzy Controller ◽  
Design Flow ◽  
High Level Synthesis ◽  
Ip Core ◽  
Inference System ◽  
System Architectures ◽  
Neuro Fuzzy ◽  
High Level

AbstractThe purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.

scholarly journals Hardware/Software Co-design Flow Using Automatic Generation of Embedded System Framework Based on Interacting FSM Model

2020 ◽  
Vol 12 (4) ◽  
pp. 859-877
Author(s):  
Arif Sasongko ◽  
Keyword(s):  
Embedded System ◽  
Automatic Generation ◽  
Design Flow ◽  
Analysis Model ◽  
System Framework ◽  
Code Generator ◽  
Finite State ◽  
The Embedded System ◽  
Automatic Code ◽  
High Level

Today’s embedded System is complex. An embedded system design project may involve of various engineering field. A rapidly-available and well-defined framework code brings advantages to the team consists of many engineers from various domains. This framework must be easy to use for communication purpose and analysis (model). This paper proposes a design flow based on a model which is high level but precise enough to use in automatic generation of the embedded system framework code. The model is flexible for rapid modification. The event driven paradigm and the FSM are used in the model. The design flow uses the model to generate framework code based on an existing platform. The work presented in this paper produces tool for the generation which is called EBGES. The proposed model describes the system as set of finite state machines (FSM) and events. This model serves for two purposes: (1) to be discussed by the developers/various engineers before deciding the platform and the architecture of the system, (2) to be used for generating the framework code. An automatic code generator is developed to produce a framework code from the model. The framework consists of (1) the FSM for every block, (2) communications between the FSMs, (3) function prototypes (for software) for function used by FSM, (4) interface of hardware module used by the FSMs, (5) instantiation of the platform. The generator software takes the model in form of annotated diagrams which are created schematically using a GUI environment. The diagrams follow UML standard. The outputs are VHDL code for hardware and C code for the software part. Example of calculator application is developed to test the tool and the flow. The generated framework code in the calculator experiment accelerated the development. Up to 51% of the code is generated automatically and 49 % of the code is written manually. The result of the experiment shows significantly improvement on design productivity which is the comes from: (1) abstraction of the behavior of subsystems/modules (HW or SW) by hiding unnecessary detail and (2) automatic generation of the framework code.

scholarly journals Optimization for Software Implementation of Fractional Calculus Numerical Methods in an Embedded System

Entropy ◽  
2020 ◽  
Vol 22 (5) ◽  
pp. 566
Author(s):  
Mariusz Matusiak
Keyword(s):  
Embedded System ◽  
Fractional Order ◽  
Numerical Algorithms ◽  
Computation Time ◽  
Optimization Methods ◽  
Optimization Techniques ◽  
Software Implementation ◽  
Software Optimization ◽  
Fractional Order Differential Equations ◽  
Non Locality

In this article, some practical software optimization methods for implementations of fractional order backward difference, sum, and differintegral operator based on Grünwald–Letnikov definition are presented. These numerical algorithms are of great interest in the context of the evaluation of fractional-order differential equations in embedded systems, due to their more convenient form compared to Caputo and Riemann–Liouville definitions or Laplace transforms, based on the discrete convolution operation. A well-known difficulty relates to the non-locality of the operator, implying continually increasing numbers of processed samples, which may reach the limits of available memory or lead to exceeding the desired computation time. In the study presented here, several promising software optimization techniques were analyzed and tested in the evaluation of the variable fractional-order backward difference and derivative on two different Arm® Cortex®-M architectures. Reductions in computation times of up to 75% and 87% were achieved compared to the initial implementation, depending on the type of Arm® core.

scholarly journals An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

2009 ◽  
Vol 2009 ◽  
pp. 1-14 ◽  
Author(s):  
Xinyu Li ◽  
Omar Hammami
Keyword(s):  
Signal Processing ◽  
Embedded System ◽  
High Performance ◽  
Chip Multiprocessors ◽  
Parallel Implementation ◽  
Data Encryption ◽  
Design Flow ◽  
Automatic Design ◽  
Single Chip ◽  
Data Parallel

Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the expected performance. And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation. An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution. Fork-Join model-based software parallelization is explored to find out the best parallelization configuration. C-based synthesis coprocessor is added to improve performance with more hardware resource usage. The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.

scholarly journals Model-Based Design of an Improved Electric Drive Controller for High-Precision Applications Based on Feedback Linearization Technique

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2954
Author(s):  
Pierpaolo Dini ◽  
Sergio Saponara
Keyword(s):  
Embedded System ◽  
Control Strategy ◽  
Feedback Linearization ◽  
Position Control ◽  
Design Flow ◽  
Control Technique ◽  
End Effector ◽  
Electrical Drives ◽  
Advanced Control ◽  
Physical Phenomena

This paper presents the design flow of an advanced non-linear control strategy, able to absorb the effects that the main causes of torque oscillations, concerning synchronous electrical drives, cause on the positioning of the end-effector of a manipulator robot. The control technique used requires an exhaustive modelling of the physical phenomena that cause the electromagnetic torque oscillations. In particular, the Cogging and Stribeck effects are taken into account, whose mathematical model is incorporated in the whole system of dynamic equations representing the complex mechatronic system, formed by the mechanics of the robot links and the dynamics of the actuators. Both the modelling procedure of the robot, directly incorporating the dynamics of the actuators and the electrical drive, consisting of the modulation system and inverter, and the systematic procedure necessary to obtain the equations of the components of the control vector are described in detail. Using the Processor-In-the-Loop (PIL) paradigm for a Cortex-A53 based embedded system, the beneficial effect of the proposed advanced control strategy is validated in terms of end-effector position control, in which we compare classic control system with the proposed algorithm, in order to highlight the better performance in precision and in reducing oscillations.

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