scholarly journals Charge Trapping Mechanism in Amorphous Si-In-Zn-O Thin-Film Transistors During Positive Bias Stress

2016 ◽  
Vol 17 (6) ◽  
pp. 380-382 ◽  
Author(s):  
Sang Yeol Lee
2016 ◽  
Vol 47 (1) ◽  
pp. 1136-1139
Author(s):  
Sung Pyo Park ◽  
Hong Jae Kim ◽  
Young Jun Tak ◽  
Seonghwan Hong ◽  
Hee Jun Kim ◽  
...  

2016 ◽  
Vol 108 (3) ◽  
pp. 033502 ◽  
Author(s):  
Yu-Hong Chang ◽  
Ming-Jiue Yu ◽  
Ruei-Ping Lin ◽  
Chih-Pin Hsu ◽  
Tuo-Hung Hou

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.


Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.


2011 ◽  
Vol 99 (17) ◽  
pp. 172106 ◽  
Author(s):  
Do Hyung Kim ◽  
Dong Youn Yoo ◽  
Hyun Kwang Jung ◽  
Dae Hwan Kim ◽  
Sang Yeol Lee

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