Hardware Trojan Detection Technique Using Frequency Characteristic Analysis of Path Delay in Application Specific Integrated Circuits

2020 ◽  
Vol 10 (2) ◽  
pp. 36-43
Author(s):  
Ha Thai Tran ◽  
Phuc Van Hoang ◽  
Tuan Ngoc Do ◽  
Duong Hai Nguyen
Keyword(s):  
Integrated Circuits ◽  
Frequency Characteristic ◽  
Integrated Circuit ◽  
Hardware Security ◽  
Hardware Trojan ◽  
Path Delay ◽  
Characteristic Analysis ◽  
Hardware Trojan Detection ◽  
Ic Manufacturing ◽  
Application Specific

 Abstract—  Since the last decade, hardware Trojan (HT) have become a serious problem for hardware security because of outsourcing trends in Integrated Circuit (IC) manufacturing. As the fabrication of IC is becoming very complex and costly, more and more chipmakers outsource their designs or parts of the fabrication process. This trend opens a loophole in hardware security, as an untrusted company could perform malicious modifications to the golden circuit at design or fabrication stages. Therefore, assessing risks and proposing solutions to detect HT are very important tasks. This paper presents a technique for detecting HT using frequency characteristic analysis of path delay. The results show that measuring with the frequency step of 0.016 MHz can detect a HT having the size of 0.2% of the original design.Tóm tắt— Từ thập niên 2010, Trojan phần cứng (HT) đã trở thành một vấn đề nghiêm trọng đối với bảo mật phần cứng, do xu hướng thuê sản xuất mạch tích hợp (Integrated Circuit - IC). Khi quá trình chế tạo IC trở nên phức tạp và tốn kém, ngày càng nhiều nhà sản xuất chip lựa chọn phương án thuê lại một phần hoặc toàn bộ thiết kế IC. Xu hướng này tạo ra lỗ hổng trong bảo mật phần cứng, vì một công ty không đáng tin cậy có thể thực hiện các sửa đổi độc hại vào trong mạch nguyên bản ở giai đoạn thiết kế hoặc chế tạo. Do đó, đánh giá rủi ro và đề xuất giải pháp phát hiện HT là một trong những nhiệm vụ hết sức quan trọng. Bài báo này trình bày một giải pháp phát hiện HT sử dụng phân tích đặc tính tần số của độ trễ đường truyền tín hiệu. Kết quả cho thấy, thực hiện khảo sát với bước tần số 0,016 MHz có thể phát hiện được HT có kích thước 0,2% so với thiết kế ban đầu. 

A Side-Channel Analysis for Hardware Trojan Detection Based on Path Delay Measurement

2018 ◽  
Vol 27 (09) ◽  
pp. 1850138 ◽  
Author(s):  
Atieh Amelian ◽  
Shahram Etemadi Borujeni
Keyword(s):  
Integrated Circuit ◽  
Side Channel ◽  
Hardware Trojan ◽  
Path Delay ◽  
Side Channel Analysis ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Delay Measurement ◽  
Channel Analysis ◽  
Circuit Function

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01[Formula: see text]ns can detect more than 80% of Trojans.

scholarly journals FPGA Realization of Deep Neural Network for Hardware Trojan Detection

2020 ◽  
Vol 9 (3) ◽  
pp. 764
Author(s):  
Varun Reddy ◽  
Nirmala Devi M
Keyword(s):  
Neural Network ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Deep Neural Network ◽  
Random Forest Classifier ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Field Programmable

With the increase in outsourcing design and fabrication, malicious third-party vendors often insert hardware Trojan (HT) in the integrated Circuits(IC). It is difficult to identify these Trojans since the nature and characteristics of each Trojan differ significantly. Any method developed for HT detection is limited by its capacity on dealing with varied types of Trojans. The main purpose of this study is to show using deep learning (DL), this problem can be dealt with some extent and the effect of deep neural network (DNN) when it is realized on field programmable gate array (FPGA). In this paper, we propose a comparison of accuracy in finding faults on ISCAS’85 benchmark circuits between random forest classifier and DNN. Further for the faster processing time and less power consumption, the network is implemented on FPGA. The results show the performance of deep neural network gets better when a large number of nets are used and faster in the execution of the algorithm. Also, the speedup of the neuron is 100x times better when implemented on FPGA with 15.32% of resource utilization and provides less power consumption than GPU.

scholarly journals Think Smart, Play Dumb: Analyzing Deception in Hardware Trojan Detection Using Game Theory

2020 ◽  
Author(s):  
Tapadhir Das
Keyword(s):  
Integrated Circuits ◽  
Repeated Game ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Learning Stage ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Utility Gain ◽  
Game Theoretic

In recent years, integrated circuits (ICs) have become<br>significant for various industries and their security has<br>been given greater priority, specifically in the supply chain.<br>Budgetary constraints have compelled IC designers to offshore manufacturing to third-party companies. When the designer gets the manufactured ICs back, it is imperative to test for potential threats like hardware trojans (HT). In this paper, a novel multilevel game-theoretic framework is introduced to analyze the interactions between a malicious IC manufacturer and the tester. In particular, the game is formulated as a non-cooperative, zerosum, repeated game using prospect theory (PT) that captures different players’ rationalities under uncertainty. The repeated game is separated into a learning stage, in which the defender<br><div>learns about the attacker’s tendencies, and an actual game stage, where this learning is used. Experiments show great incentive for the attacker to deceive the defender about their actual rationality by “playing dumb” in the learning stage (deception). This scenario is captured using hypergame theory to model the attacker’s view of the game. The optimal deception rationality of the attacker is analytically derived to maximize utility gain. For the defender, a first-step deception mitigation process is proposed to thwart the effects of deception. Simulation results show that the attacker can profit from the deception as it can successfully insert HTs in the manufactured ICs without being detected.</div><div><br></div><div>This paper has been accepted for publication in <b>IEEE Cyber Science Conference 2020</b><br></div>

Hardware Trojan Detection Using the Order of Path Delay

2018 ◽  
Vol 14 (3) ◽  
pp. 1-23 ◽  
Author(s):  
Xiaotong Cui ◽  
Elnaz Koopahi ◽  
Kaijie Wu ◽  
Ramesh Karri
Keyword(s):  
Hardware Trojan ◽  
Path Delay ◽  
Hardware Trojan Detection ◽  
Trojan Detection
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