The nonlinear relationship between financial flexibility and enterprise risk-taking during the COVID-19 pandemic in Taiwan?s semiconductor industry

Research background: Risk-taking is the basis for sustainable development of enterprise. It was clear that the influence COVID-19 epidemic on the global market economy has increased operational risks for businesses. The semiconductor industry has high operating risks and financial risks. Moderate financial flexibility (FF) can improve the ability of semiconductor enterprises to acquire financial resources in real time, calmly cope with the impact of uncertainties in operation, improve investment opportunities, and enhance sustainable operation. It is therefore interesting to study the influence of FF on enterprise risk-taking (ERT). Purpose of the article: The aim of the contribution is to explore the effect of FF on ERT within Taiwan?s semiconductor industry amid the COVID-19 pandemic period, and investigate whether ERT varies with semiconductor industry characteristic. Methods: Data from first three quarters of 2020, from multinational semiconductor firms listed on the Taiwan Stock Exchange (TSE), were collected and analyzed. Fixed effects regression with heteroscedasticity adjustment used to evaluate the influence of FF on the ERT of Taiwan?s semiconductor industry. Furthermore, in order to corroborate and support the reliability of the results, this research also used the different measures of ERT and Quantile regression (median regression) in the research model to check the robustness. Findings & value added: Empirical results indicate that FF has a U-shaped effect on ERT for multinational semiconductor firms listed on the TSE, particularly within the integrated circuits (IC) manufacturing industry. Additionally, FF also has a U-shaped effect on ERT for the asset-light semiconductor and IC manufacturing industries. This article also suggests that for the asset-light semiconductor and IC manufacturing industries, the optimal inflection points are 1.1397 and 0.9729, respectively. Based on the consequences of this study, it is suggested that Taiwan?s semiconductor industry should reasonably maintain FF and focus on the liquidity risk management for the long term value added, even after the COVID-19 pandemic period.

S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I_ON of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V_DD to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V_DD scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

S-curve Engineering for ON-state Performance using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I_ON of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V_DD to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V_DD scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>

Performance Analysis of Adiabatic Vedic Multipliers

Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

Friction-Induced Nanofabrication: A Review

As the bridge between basic principles and applications of nanotechnology, nanofabrication methods play significant role in supporting the development of nanoscale science and engineering, which is changing and improving the production and lifestyle of the human. Photo lithography and other alternative technologies, such as nanoimprinting, electron beam lithography, focused ion beam cutting, and scanning probe lithography, have brought great progress of semiconductor industry, IC manufacturing and micro/nanoelectromechanical system (MEMS/NEMS) devices. However, there remains a lot of challenges, relating to the resolution, cost, speed, and so on, in realizing high-quality products with further development of nanotechnology. None of the existing techniques can satisfy all the needs in nanoscience and nanotechnology at the same time, and it is essential to explore new nanofabrication methods. As a newly developed scanning probe microscope (SPM)-based lithography, friction-induced nanofabrication provides opportunities for maskless, flexible, low-damage, low-cost and environment-friendly processing on a wide variety of materials, including silicon, quartz, glass surfaces, and so on. It has been proved that this fabrication route provides with a broad application prospect in the fabrication of nanoimprint templates, microfluidic devices, and micro/nano optical structures. This paper hereby involved the principals and operations of friction-induced nanofabrication, including friction-induced selective etching, and the applications were reviewed as well for looking ahead at opportunities and challenges with nanotechnology development. The present review will not only enrich the knowledge in nanotribology, but also plays a positive role in promoting SPM-based nanofabrication.

Application of Stereolithography Based 3D Printing Technology in Investment Casting

Advanced methods for manufacturing high quality parts should be used to ensure the production of competitive products for the world market. Investment casting (IC) is a process where a wax pattern is used as a sacrificial pattern to manufacture high precision casting of solid metal parts. Rapid casting is in turn, a technique that eases the IC process by combining additive manufacturing (AM) technologies with IC. The use of AM technologies to create patterns for new industrial products is a unique opportunity to develop cost-effective methods for producing investment casting parts in a timely manner. Particularly, stereolithography (SLA) based AM is of interest due to its high dimensional accuracy and the smooth surface quality of the printed parts. From the first appearance of commercially available SLA printers in the market, it took a few decades until desktop SLA printers became available to consumers at a reasonable price. Therefore, the aim of this review paper is to analyze the state-of-the-art and applicability of SLA based 3D printing technology in IC manufacturing, as SLA based AM technologies have been gaining enormous popularity in recent times. Other AM techniques in IC are also reviewed for comparison. Moreover, the SLA process parameters, material properties, and current issues are discussed.