Mathematical logic: construction of logic circuits from logical elements in Maple

В статье рассматриваются возможности применения библиотеки Logic системы компьютерной алгебры Maple в аспекте компьютерного моделирования логических схем в различных базисах. Смоделированы основные логические элементы в Maple. На конкретном примере детально представлен алгоритм построения логической схемы в различных базисах. The article discusses the possibilities of using the Logic library of the Maple computer algebra system in the aspect of computer modeling of logic circuits in various bases. Basic logic gates are modeled in Maple. On a specific example, an algorithm for constructing a logical circuit in various bases is presented in detail.

CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications

Satellite communications are a well-established research area in which the main innovation of last decade has been the use of multi-carrier modulations and more robust channel coding techniques. However, in recent years, novel advanced signal processing has started being developed for these communications due to the increase in the signal processing capacity of transmitters and receivers. Although signal processing capabilities are increasing, they are still constrained by large limitations because these techniques need to be implemented in real hardware, thus making complexity a matter of critical importance. Therefore, this paper presents the design and implementation of a transmitter with adaptable coding and modulation on a field-programmable-gate-array (FPGA). The main motivation came from the standard CCSDS 131.2-B-1 which recommends that such a novel transmitter which has to date not been implemented in a real system The system was modeled by MATLAB with the purpose of being programmed in VHDL following the AXI-stream protocol between components. Behavioral simulation results were obtained in VIVADO and compared with MATLAB for verification purposes. The transmitter logical circuit was synthesized in a FPGA Zynq Ultrascale RFSoC ZU28DR, showing low resource consumption and correct functioning, leading us to conclude that the deployment of new communication systems in state-of-the-art hardware in satellite communications is justified.

On Heaviside Binary Logic: a Mathematical Characterization and its Applications

In this work, the existence of a correspondence between fundamental programming language control structures and mathematical formulation is proven. The proposed interpretation is given through a well-defined logical circuit analytical expression. Relevant geometrical applications having wide implications in engineering branches are presented together with a new Penalty Method for constrained optimization problems handling.

Algorithms for partitioning logical circuits into subcircuits

The problem of partitioning a logical circuit into subcircuits is considered. It is of great importance when performing optimization transformations in the process of circuit synthesis. The brief review of partitioning methods and algorithms is given, and two groups of algorithms are identified: constructive and iterative one. The interpretation of a logical circuit in the form of a graph is presented. The problem of partitioning in terms of a graph-theoretic model is defined and some algorithms for solving the partitioning problem are proposed. Logic circuit functions are defined by a system of logical equations. Algorithms perform the partitioning the system of logical equations into subsystems with the restrictions of the number of input and output variables. The data structures to execute the algorithms are defined. Various types of equations connections, obtaining better solutions for partitioning are described. The problems of the use of partitioning algorithms to improve the quality of the circuit at the stage of technology-independent optimization are investigated. The results of an experimental study carried out by the BDD optimization procedure for the functional description of the circuit and LeonardoSpectrum synthesis confirm the effectiveness of the developed algorithms. The algorithms are implemented as partitioning circuit procedures in the experimental FLC system for logical design.

On Heaviside Binary Logic: a Mathematical Characterization and its Applications

In this work, the existence of a correspondence between fundamental programming language control structures and mathematical formulation is proven. The proposed interpretation is given through a well-defined logical circuit analytical expression. Relevant geometrical applications having wide implications in engineering branches are presented together with a new Penalty Method for constrained optimization problems handling.

On Heaviside Binary Logic: a Mathematical Characterization and its Applications

In this work, the existence of a correspondence between fundamental programming language control structures and mathematical formulation is proven. The proposed interpretation is given through a well-defined logical circuit analytical expression. Relevant geometrical applications having wide implications in engineering branches are presented together with a new Penalty Method for constrained optimization problems handling.

Evolutionary Dendritic Neural Model for Classification Problems

In this paper, an evolutionary dendritic neuron model (EDNM) is proposed to solve classification problems. It utilizes synapses and dendritic branches to implement the nonlinear computation. Distinct from the classical dendritic neuron model (CDNM) trained by the backpropagation (BP) algorithm, the proposed EDNM is trained by a metaheuristic cuckoo search (CS) algorithm instead, which has been regarded as a global searching algorithm. CS algorithm enables EDNM to avoid several disadvantages, such as slow convergence, trapping into local minimum, and being sensitive to initial values. To evaluate the performance of EDNM, we compare it with a multilayer perceptron (MLP) and CDNM on two benchmark classification problems. The experimental results demonstrate that EDNM is superior to MLP and CDNM in terms of accuracy rate, receiver operator characteristic curve (ROC), and convergence speed. In addition, the neural structure of EDNM can be replaced by a logical circuit completely, which can be implemented in hardware easily. The corresponding experimental results also verify the effectiveness of the logical circuit classifier.

Optimal production of microprocessors to increase the life quality

This paper discusses needs for the automation of the underdevelopment communities. The novelty of this research is the link between production of microprocessors and increasing of the life quality. This study highlights the importance of efficient and economic architecture of logical circuits for the automation. The aim of this research is to produce a logical circuit, which includes suitable gates. The circuit will be embedded in the automatic devices as a microprocessor to cause programmed functions. This research reports analytically a workshop method to build the circuit. It uses an assembly card and required gates. Then, it suggests certain VHDL codes to drive a motor. The workshop presents the configuration schemes and connection board for every gate. In addition, it shows a schematic wiring diagram of the circuit. Finally, the economic analysis proves the mass production of the circuit will enhance the automation and consequently the quality of life. The outcome of this research is a helpful experience to the engineers, manufacturers and students of the relevant disciplines to resolve the inequality in the use of the modern technologies.