Design Techniques for Power-Gated Nanoscale Low Power Circuits

Background: With the shrinking device-sizes in the present day world, the leakage power of the devices has also been increased significantly. Several techniques have been proposed to minimize the leakage power. However, the techniques have certain limitations, such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit. Objective: In this paper, we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits. Methods: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology. Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques, respectively. The behavior of the circuit techniques has also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimize leakage power and the on-time delay significantly. A layout of the section of the proposed circuit has also been drawn which occupies the chip area of 2.37 µm2. Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in the noise as well as delay. In this paper, we propose leakage minimization techniques for the distributed sleep transistor network. The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in noise as well as delay. The technique also reduces the leakage power significantly.

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Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.203.469 ◽

2012 ◽

Vol 203 ◽

pp. 469-473

Author(s):

Ruei Chang Chen ◽

Shih Fong Lee

Keyword(s):

Low Power ◽

High Performance ◽

Low Voltage ◽

Design Flow ◽

Total Power ◽

Cmos Process ◽

Low Power Circuits ◽

Class D ◽

Total Power Consumption ◽

Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

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W2B: High Performance Low Power Circuits

2018 31st IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2018.8618573 ◽

2018 ◽

Keyword(s):

Low Power ◽

High Performance ◽

Low Power Circuits ◽

Power Circuits

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Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.12.11280 ◽

2018 ◽

Vol 7 (2.12) ◽

pp. 205

Author(s):

T Vasudeva Reddy ◽

Dr B.K. Madhavi

Keyword(s):

Low Power ◽

High Performance ◽

Supply Voltage ◽

Process Variations ◽

Primary Objective ◽

Total Power ◽

Threshold Region ◽

Major Power ◽

Low Power Circuits ◽

Power Circuits

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.

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F2B: Low Power Circuits II

2018 31st IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2018.8618522 ◽

2018 ◽

Keyword(s):

Low Power ◽

Low Power Circuits ◽

Power Circuits

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Comparative analysis of SRAM cell with leakage power reduction approaches

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.7.11083 ◽

2018 ◽

Vol 7 (2.7) ◽

pp. 863

Author(s):

Damarla Paradhasaradhi ◽

Kollu Jaya Lakshmi ◽

Yadavalli Harika ◽

Busa Ravi Teja Sai ◽

Golla Jayanth Krishna

Keyword(s):

Low Power ◽

Power Dissipation ◽

Low Voltage ◽

Power Saving ◽

Vital Role ◽

Power Reduction ◽

Leakage Power ◽

Access Time ◽

Chip Area ◽

Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

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