Unique Analysis Approach to Bridge-T Network using Floating Admittance Matrix Method”

The RC bridge-T Circuit are sometimes preferred for radio frequency applications as it does not require transformer (inductive coupling). The uses of the resistance-capacitance form of the network permits a wide tuning range. The article aims to develop a band pass filter's mathematical model using the Floating Admittance Matrix (FAM) approach. Both types of RC bridge-T network form the band-pass filters. The use of the conventional methods of analysis such as KCL, KVL, Thevenin's, Norton's depends on its suitability for the type of the particular circuit. The proposed mathematical modeling scheme using the floating admittance matrix approach is unique, and the same can be used for all types of circuits. This method is suitable to use the partitioning technique for large network. The sum property of all the elements of any row or any column equal to zero provides the assurance to proceed further for analysis or re-observe the very first equation. This saves time and energy. The FAM method presented here is so simple that anybody with slight knowledge of electronics but understating the matrix maneuvering, can analyze any circuit to derive all types of its transfer functions. The mathematical modeling using the FAM approach provides leverage to the designer to comfortably adjust their design at any stage of analysis. These statements provide compelling reasons for the adoption of the proposed process and demonstrate its benefits. The theoretically obtained equations meet the expected result for the RC bridge-T network. Its response peaks at the theoretically obtained value of the frequency. The simulated results are in agreement with the topological explanations and expectations.

A Novel Fast-Locking ADPLL Based on Bisection Method

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.