2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
Latest Publications

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9781538642603

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Machine learning further improving place and route QoR

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373257 ◽

2018 ◽

Author(s):

Weibin Ding

Keyword(s):

Machine Learning ◽

Place And Route

Optimization of threshold logic networks with ODC-based node merging

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373232 ◽

2018 ◽

Cited By ~ 1

Author(s):

Fu-Lian Wong ◽

Li-Cheng Zheng ◽

Yung-Chih Chen

Keyword(s):

Threshold Logic

Accurate and fast obstacle detection method for automotive applications based on stereo vision

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373249 ◽

2018 ◽

Cited By ~ 1

Author(s):

Yi-Chin Tsai ◽

Kuan-Hung Chen ◽

Yun Chen ◽

Jih-Hsiang Cheng

Keyword(s):

Stereo Vision ◽

Detection Method ◽

Obstacle Detection ◽

Automotive Applications

Systematic co-optimization from chip design, process technology to systems for GPU AI chip

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373280 ◽

2018 ◽

Cited By ~ 1

Author(s):

John R Hu ◽

James Chen ◽

Boon-khim Liew ◽

Yanfeng Wang ◽

Lianxi Shen ◽

...

Keyword(s):

Design Process ◽

Process Technology ◽

Chip Design

A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373261 ◽

2018 ◽

Cited By ~ 1

Author(s):

Fangyu Mao ◽

Yan Lu ◽

U Seng-Pan ◽

Rui P. Martins

Keyword(s):

Wireless Power Transfer ◽

Power Transfer ◽

Wireless Power ◽

Delay Compensation ◽

Voltage Doubler

The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373268 ◽

2018 ◽

Author(s):

Feng Zhang ◽

Dong-Yu Fan ◽

Qi-Peng Lin ◽

Qiang Huo ◽

Yun Li ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Resistance Switching ◽

Access Memory ◽

Look Up Table

Using approximate circuits to counter process imperfections in CNFET based circuits

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373267 ◽

2018 ◽

Cited By ~ 1

Author(s):

Kaship Sheikh ◽

Lan Wei

Keyword(s):

Counter Process

A learning-based methodology for routability prediction in placement

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373272 ◽

2018 ◽

Cited By ~ 3

Author(s):

Li-Chin Chen ◽

Chien-Chia Huang ◽

Yao-Lin Chang ◽

Hung-Ming Chen

Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM)

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373239 ◽

2018 ◽

Cited By ~ 1

Author(s):

Subagaran Letchumanan ◽

Terrence Huat Hin Tan ◽

Yee Pheng Gan ◽

Sai Leong Wong

Keyword(s):

Production System ◽

Test Method ◽

System Level ◽

Test Cost ◽

Adaptive Test

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2018.8373224 ◽

2018 ◽

Author(s):

Ryosuke Noguchi ◽

Kosuke Furuichi ◽

Hiromu Uemura Toshiyuki Inoue ◽

Akira Tsuchiya ◽

Keiji Kishine ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Flip Flop

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Machine learning further improving place and route QoR

Optimization of threshold logic networks with ODC-based node merging

Accurate and fast obstacle detection method for automotive applications based on stereo vision

Systematic co-optimization from chip design, process technology to systems for GPU AI chip

A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems

The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory

Using approximate circuits to counter process imperfections in CNFET based circuits

A learning-based methodology for routability prediction in placement

Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM)

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
Latest Publications