TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip

The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques.

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Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2017.6355 ◽

2017 ◽

Vol 14 (1) ◽

pp. 511-516

Author(s):

Sharmila Durai ◽

Rangarajan Parthasarathy

Keyword(s):

Rejection Rate ◽

System On Chip ◽

Key Generation ◽

Quantum Fourier Transform ◽

Ip Core ◽

Authentication Mechanism ◽

Novel Method ◽

On Chip ◽

The Individual ◽

Test Wrapper

System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).

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Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

Journal of Intelligent & Fuzzy Systems ◽

10.3233/jifs-201691 ◽

2020 ◽

pp. 1-13

Author(s):

Gokul Chandrasekaran ◽

P.R. Karthikeyan ◽

Neelam Sanjeev Kumar ◽

Vanchinathan Kumarasamy

Keyword(s):

Ant Colony Optimization ◽

Artificial Bee Colony ◽

Optimization Algorithms ◽

System On Chip ◽

Test Time ◽

Test Scheduling ◽

Bee Colony ◽

Ant Lion Optimization ◽

Ant Lion ◽

On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

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Fine-Grain Dynamic Energy Tracking for System on Chip

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2013.2258246 ◽

2013 ◽

Vol 60 (6) ◽

pp. 356-360 ◽

Cited By ~ 2

Author(s):

I. Mansouri ◽

P. Benoit ◽

L. Torres ◽

F. Clermidy

Keyword(s):

System On Chip ◽

Fine Grain ◽

On Chip

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Measuring Static Parameters of Embedded ADC Core

Journal of Electrical Engineering ◽

10.2478/v10187-011-0013-3 ◽

2011 ◽

Vol 62 (2) ◽

pp. 80-86

Author(s):

Franc Novak ◽

Peter Mrak ◽

Anton Biasizzo

Keyword(s):

Feasibility Study ◽

Theoretical Background ◽

System On Chip ◽

Test Time ◽

Hardware Overhead ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

The Impact ◽

Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

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Fine-grain power management in manycore processor and System-on-Chip (SoC) designs

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2015.7372564 ◽

2015 ◽

Cited By ~ 7

Author(s):

Vivek De

Keyword(s):

Power Management ◽

System On Chip ◽

Fine Grain ◽

On Chip

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Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques

Neural Computing and Applications ◽

10.1007/s00521-019-04039-6 ◽

2019 ◽

Vol 32 (9) ◽

pp. 5303-5312 ◽

Cited By ~ 1

Author(s):

Gokul Chandrasekaran ◽

Sakthivel Periyasamy ◽

Karthikeyan Panjappagounder Rajamanickam

Keyword(s):

Artificial Intelligence ◽

System On Chip ◽

Test Time ◽

Test Scheduling ◽

On Chip

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Study on Bus Assignment Algorithm for SOC Test

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.713-715.1252 ◽

2015 ◽

Vol 713-715 ◽

pp. 1252-1255

Author(s):

Xiao Min Li ◽

Shuang Hua Huang

Keyword(s):

System On Chip ◽

Test Time ◽

Main Concern ◽

Superposition Method ◽

Compression Process ◽

Test Access Mechanism ◽

Soc Test ◽

Assignment Algorithm ◽

Temperature Superposition ◽

On Chip

The main concern is over rising temperature during the testing of complex system-on-chip (SOC), this paper studies SOC wrapper and test access mechanism (TAM), and proposes an improved algorithm of TAM assignment under the constraints of temperature. The algorithm uses temperature superposition method and adds compression process. This algorithm can find the test structure that uses shorter test time.

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ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea9020019 ◽

2019 ◽

Vol 9 (2) ◽

pp. 19 ◽

Cited By ~ 1

Author(s):

Harikrishna Parmar ◽

Usha Mehta

Keyword(s):

Communication Network ◽

Network On Chip ◽

Test Time ◽

Test Scheduling ◽

Power Budget ◽

Power Efficient ◽

Efficient Test ◽

Ip Cores ◽

On Chip ◽

The Individual

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

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Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip

Materials Science Forum ◽

10.4028/www.scientific.net/msf.663-665.670 ◽

2010 ◽

Vol 663-665 ◽

pp. 670-673

Author(s):

Zhong Liang Pan ◽

Ling Chen

Keyword(s):

Genetic Algorithm ◽

System On Chip ◽

Test Time ◽

Test Scheduling ◽

Scheduling Problem ◽

Good Test ◽

Cellular Genetic Algorithm ◽

Scheduling Method ◽

On Chip ◽

Feasible Solutions

The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

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