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Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 22
Author(s):  
Xiangbin Wang ◽  
Yushan Sun ◽  
Lei Wan ◽  
Hongyu Bian ◽  
Xiangrui Ran

A water conveyance tunnel is narrow and enclosed with a complex distribution of flow field. The performance of sensors such as Doppler log, magnetic compass, sonar, and depth gauge used by conventional underwater vehicles in the tunnel is greatly affected and can even fail. Aiming at the special operating environment and operational requirements of water conveyance tunnels, this paper designed an architecture suitable for pressurized water conveyance tunnel-detection autonomous underwater vehicles (AUVs). The tunnel-detection AUV (called AUV-T in this paper) with the architecture proposed in this paper could easily and smoothly complete inspection tasks in water conveyance tunnels, and field tests have verified the effectiveness of the architecture. Since an AUV in a water conveyance tunnel cannot go to the surface to rescue itself, in order to ensure its safety we designed the heterogeneous dual-CPU (Central Processing Unit) hot redundancy system based on dual communication lines. The reliability analysis showed that the system can significantly reduce the probability of AUV failure and ensure that the AUV can still be recovered even if it fails in the tunnel.


Author(s):  
Shengwen Zhou ◽  
Jing Chen ◽  
Chun Xiao ◽  
Guangqiang Li
Keyword(s):  

Author(s):  
Alejandro Peraza ◽  
Andrew Freiha ◽  
Carlos Hernandez ◽  
Kris Whaley ◽  
Thomas Barbarito ◽  
...  

2020 ◽  
Vol 213 ◽  
pp. 02006
Author(s):  
Qiao Sun ◽  
Shaokun Jia ◽  
Jie Zhang ◽  
Kunpeng Zhao ◽  
Zhixiang Li ◽  
...  

Dual CPU redundant operation of PLC is of great significance to the reliability of industrial automation control system. In view of the problems existing in the traditional dual CPU PLC redundancy control mode based on hardware strategy, this paper proposes a dual CPU redundancy control idea based on software strategy, and describes in detail the specific scheme of Dual CPU redundancy software design using A-B ControlLogix series PLC.


SPE Journal ◽  
2014 ◽  
Vol 19 (04) ◽  
pp. 716-725 ◽  
Author(s):  
Larry S.K. Fung ◽  
Mohammad O. Sindi ◽  
Ali H. Dogru

Summary With the advent of the multicore central-processing unit (CPU), today's commodity PC clusters are effectively a collection of interconnected parallel computers, each with multiple multicore CPUs and large shared random access memory (RAM), connected together by means of high-speed networks. Each computer, referred to as a compute node, is a powerful parallel computer on its own. Each compute node can be equipped further with acceleration devices such as the general-purpose graphical processing unit (GPGPU) to further speed up computational-intensive portions of the simulator. Reservoir-simulation methods that can exploit this heterogeneous hardware system can be used to solve very-large-scale reservoir-simulation models and run significantly faster than conventional simulators. Because typical PC clusters are essentially distributed share-memory computers, this suggests that the use of the mixed-paradigm parallelism (distributed-shared memory), such as message-passing interface and open multiprocessing (MPI-OMP), should work well for computational efficiency and memory use. In this work, we compare and contrast the single-paradigm programming models, MPI or OMP, with the mixed paradigm, MPI-OMP, programming model for a class of solver method that is suited for the different modes of parallelism. The results showed that the distributed memory (MPI-only) model has superior multicompute-node scalability, whereas the shared memory (OMP-only) model has superior parallel performance on a single compute node. The mixed MPI-OMP model and OMP-only model are more memory-efficient for the multicore architecture than the MPI-only model because they require less or no halo-cell storage for the subdomains. To exploit the fine-grain shared memory parallelism available on the GPGPU architecture, algorithms should be suited to the single-instruction multiple-data (SIMD) parallelism, and any recursive operations are serialized. In addition, solver methods and data store need to be reworked to coalesce memory access and to avoid shared memory-bank conflicts. Wherever possible, the cost of data transfer through the peripheral component interconnect express (PCIe) bus between the CPU and GPGPU needs to be hidden by means of asynchronous communication. We applied multiparadigm parallelism to accelerate compositional reservoir simulation on a GPGPU-equipped PC cluster. On a dual-CPU-dual-GPGPU compute node, the parallelized solver running on the dual-GPGPU Fermi M2090Q achieved up to 19 times speedup over the serial CPU (1-core) results and up to 3.7 times speedup over the parallel dual-CPU X5675 results in a mixed MPI + OMP paradigm for a 1.728-million-cell compositional model. Parallel performance shows a strong dependency on the subdomain sizes. Parallel CPU solve has a higher performance for smaller domain partitions, whereas GPGPU solve requires large partitions for each chip for good parallel performance. This is related to improved cache efficiency on the CPU for small subdomains and the loading requirement for massive parallelism on the GPGPU. Therefore, for a given model, the multinode parallel performance decreases for the GPGPU relative to the CPU as the model is further subdivided into smaller subdomains to be solved on more compute nodes. To illustrate this, a modified SPE5 (Killough and Kossack 1987) model with various grid dimensions was run to generate comparative results. Parallel performances for three field compositional models of various sizes and dimensions are included to further elucidate and contrast CPU-GPGPU single-node and multiple-node performances. A PC cluster with the Tesla M2070Q GPGPU and the 6-core Xeon X5675 Westmere was used to produce the majority of the reported results. Another PC cluster with the Tesla M2090Q GPGPU was available for some cases, and the results are reported for the modified SPE5 (Killough and Kossack 1987) problems for comparison.


2013 ◽  
Vol 803 ◽  
pp. 480-484
Author(s):  
Hai Tao Ma ◽  
Shu Fan Ma ◽  
Ying Yu

According to the characteristics of argon oxygen refining ferroalloy production process, design two lays control structure. The first lay is centralized monitoring level, adopte dual-CPU IPC to deal with the complex data operations and centralized monitoring operations. The second lay is process control level, use S7-300 PLC of siemens series, the control system is divided into six subsystems. The subsystem and the central controller share with three sets of PLC, to carry out automatic control for the devices of production line. And complete DCS control system design of argon oxygen refining ferroalloy production process, the system have been put into production, stable and reliable, build a hardware platform to achieve energy-saving control strategies of production process.


2012 ◽  
Vol 616-618 ◽  
pp. 2038-2043
Author(s):  
Li Hua Liu ◽  
Ming Sun ◽  
Shu Jian Zhang

At present, China is vigorously developing the smart grid, due to the immaturity of the intelligent circuit breaker, a totally new device is introduced in the process layer to ensure the realization of intellectualization of primary equipment in the intelligent substation: the. The intelligent terminal is an interface of primary equipment and secondary equipment in intelligent substation system realizing the intelligent transformation of the traditional primary equipment, which is also the optimal solution to the traditional switch and transformer interface problems of intelligent substation. The intelligent terminal devices of 126KVGIS are designed in this paper, the design process adopts the method of ARM+FPGA dual-CPU structure,which makes the intelligent terminal have an efficient and rapid processing capacity so as to satisfy the requirement of practical application. Starting from the modularization structure design, function of each module, circuit design and implementation method were introduced in detail. A hardware platform was established according to the design. Finally, the article confirmed the correctness of the hardware platform primarily through experimental method.


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