An Efficient Algorithm for Solving Minimum Cost Flow Problem with Complementarity Slack Conditions

This paper presents an algorithm for solving a minimum cost flow (MCF) problem with a dual approach. The algorithm holds the complementary slackness at each iteration and finds an augmenting path by updating node potential iteratively. Then, flow can be augmented at the original network. In contrast to other popular algorithms, the presented algorithm does not find a residual network, nor find a shortest path. Furthermore, our algorithm holds information of node potential at each iteration, and we update node potential within finite iterations for expanding the admissible network. The validity of our algorithm is given. Numerical experiments show that our algorithm is an efficient algorithm for the MCF problem, especially for the network with a small interval of cost of per unit flow.

Analysis of Write Recovery Time Degradation Caused by Adjacent Storage Node Data in DRAM

As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.

LEAKAGE POWER REDUCTION IN SRAM AT NANOSCALE

In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45 nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.