etch stop layer
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2021 ◽  
Author(s):  
Amirkianoosh Kiani ◽  
Krishnan Venkatakrishnan ◽  
Bo Tan ◽  
Venkat Venkataramanan

In this study we report a new method for maskless lithography fabrication process by a combination of direct silicon oxide etch-stop layer patterning and wet alkaline etching. A thin layer of etch-stop silicon oxide of predetermined pattern was first generated by irradiation with high repetition (MHz) ultrafast (femtosecond) laser pulses in air and at atmospheric pressure. The induced thin layer of silicon oxide is used as an etch stop during etching process in alkaline etchants such as KOH. Our proposed method has the potential to enable low-cost, flexible, high quality patterning for a wide variety of application in the field of micro- and nanotechnology, this technique can be leading to a promising solution for maskless lithography technique. A Scanning Electron Microscope (SEM), optical microscopy, Micro-Raman, Energy Dispersive X-ray (EDX) and X-ray diffraction spectroscopy were used to analyze the silicon oxide layer induced by laser pulses.


Author(s):  
Roger Loo ◽  
Anne Jourdain ◽  
Gianluca Rengo ◽  
Clement Porret ◽  
Andriy Hikavyy ◽  
...  

2020 ◽  
Vol 32 (23) ◽  
pp. 10055-10065
Author(s):  
David R. Zywotko ◽  
Omid Zandi ◽  
Jacques Faguet ◽  
Paul R. Abel ◽  
Steven M. George

2020 ◽  
Vol MA2020-02 (22) ◽  
pp. 1640-1640
Author(s):  
Roger Loo ◽  
Anne Jourdain ◽  
Gianluca Rengo ◽  
Clement Porret ◽  
Andriy Yakovitch Hikavyy ◽  
...  

2020 ◽  
Vol 98 (4) ◽  
pp. 157-166
Author(s):  
Roger Loo ◽  
Anne Jourdain ◽  
Gianluca Rengo ◽  
Clement Porret ◽  
Andriy Yakovitch Hikavyy ◽  
...  

2020 ◽  
Vol 31 (13) ◽  
pp. 10078-10083
Author(s):  
Qiang Xu ◽  
Wenjuan Xiong ◽  
Guilei Wang ◽  
Tianchun Ye
Keyword(s):  

Author(s):  
Wangran Wu ◽  
Helong Geng ◽  
Feng Lin ◽  
Shuxian Chen ◽  
Ruibin Cao ◽  
...  
Keyword(s):  

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 414
Author(s):  
Yuan ◽  
Jiang ◽  
Sun ◽  
Chen ◽  
Zhu ◽  
...  

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.


2019 ◽  
Vol 34 (1) ◽  
pp. 7-13
Author(s):  
万云海 WAN Yun-hai ◽  
邹志翔 ZOU Zhi-xiang ◽  
林 亮 LIN Liang ◽  
杨成绍 YANG Cheng-shao ◽  
黄寅虎 HUANG Yin-hu ◽  
...  

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