Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

2019 ◽  
Vol 17 (05) ◽  
pp. 1950048
Author(s):  
Abdollah Norouzi Doshanlou ◽  
Majid Haghparast ◽  
Mehdi Hosseinzadeh ◽  
Midia Reshadi
Keyword(s):  
System Performance ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Constant Input ◽  
Comparison Results ◽  
Garbage Output ◽  
First Time

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

2020 ◽  
Vol 12 ◽  
Author(s):  
Heranmoy Maity ◽  
Sudipta Banerjee ◽  
Raton Mistry ◽  
Parna Kundu ◽  
Kriti Ojha ◽  
...  
Keyword(s):  
Quantum Circuit ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Garbage Output ◽  
Feynman Gate ◽  
Cost Efficient ◽  
Optimized Code ◽  
Logic Functions ◽  
Very High

Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

2020 ◽  
Vol 12 (3) ◽  
pp. 146-148
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Arup K. Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Optimized Design ◽  
Quantum Cost ◽  
Constant Input ◽  
Logic Block ◽  
Reversible Gate ◽  
Garbage Output

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

2018 ◽  
Vol 16 (07) ◽  
pp. 1850061 ◽  
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Logic Gate ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Reversible Circuit ◽  
Reversible Gate ◽  
Garbage Output ◽  
Feynman Gate

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

scholarly journals Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

2021 ◽  
Vol 23 (09) ◽  
pp. 1313-1325
Author(s):  
Gobinda Karmakar ◽  
◽  
Dr. Saroj Kumar Biswas ◽  
Dr. Ardhendu Mandal ◽  
Arijit Bhattacharya ◽  
...  
Keyword(s):  
Research Area ◽  
Sequential Circuits ◽  
Quantum Cost ◽  
Efficient Design ◽  
Hardware Complexity ◽  
Constant Input ◽  
Reversible Computing ◽  
Main Challenge ◽  
Comparative Review ◽  
Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

scholarly journals The Susceptibility of Meningococci to the Antimicrobial Agents in Moscow 2006 - 2015

2016 ◽  
Vol 15 (3) ◽  
pp. 7-14 ◽  
Author(s):  
M. A. Koroleva ◽  
I. S. Koroleva ◽  
I. M. Zakroeva ◽  
I. M. Gruber
Keyword(s):  
Cerebrospinal Fluid ◽  
Continuous Monitoring ◽  
Antimicrobial Agents ◽  
Meningococcal Infection ◽  
Test Results ◽  
Prognostic Criteria ◽  
Comparison Results ◽  
Moderately Resistant ◽  
First Time

Relevance. One of the prognostic criteria meningococcal infection (MI) epidemic status process is the increasing number of resistant to antibiotics meningococcal strains. Aim of this study was to investigate the dynamics of invasive strains of N. meningitidis susceptibility to antibiotics in Moscow in 2006 - 2015. Materials and methods. Studied 98 strains of N. meningitidis, isolated from blood and cerebrospinal fluid of patients with MI. The study changes of sensitivity N. meningitidis to antibiotics was occured in two periods: first -2006 - 2011 and second - 2012 - 2015. The MIC was determined by E-test. Results. In the present study revealed for the first time the Russian strains of N. meningitidis, moderately resistant to penicillin (5 strains) and resistant to rifampicin (3 strains). Among the studied strains were not found resistant to ceftriaxone, ciprofloxacin, tetracycline and chloramphenicol. Discussion. Comparison results two study periods allowed to reveal the dynamics of increasing the sensitivity of N. meningitidis to antibiotics, which confirms the decline in meningococcal virulence, and as a result, continued interepidemic MI period. Conclusions. Despite the decline antibakterial resistance is required continuous monitoring.

A novel enhanced quantum image representation based on bit-planes for log-polar coordinates

2022 ◽  
Vol 22 (1&2) ◽  
pp. 17-37
Author(s):  
Xiao Chen ◽  
Zhihao Liu ◽  
Hanwu Chen ◽  
Liang Wang
Keyword(s):  
Color Image ◽  
Image Representation ◽  
Polar Coordinates ◽  
Quantum Cost ◽  
Color Information ◽  
Simulation Experiments ◽  
Quantum Image ◽  
Comparison Results ◽  
Bit Planes ◽  
Quantum Image Representation

Quantum image representation has a significant impact in quantum image processing. In this paper, a bit-plane representation for log-polar quantum images (BRLQI) is proposed, which utilizes $(n+4)$ or $(n+6)$ qubits to store and process a grayscale or RGB color image of $2^n$ pixels. Compared to a quantum log-polar image (QUALPI), the storage capacity of BRLQI improves 16 times. Moreover, several quantum operations based on BRLQI are proposed, including color information complement operation, bit-planes reversing operation, bit-planes translation operation and conditional exchange operations between bit-planes. Combining the above operations, we designed an image scrambling circuit suitable for the BRLQI model. Furthermore, comparison results of the scrambling circuits indicate that those operations based on BRLQI have a lower quantum cost than QUALPI. In addition, simulation experiments illustrate that the proposed scrambling algorithm is effective and efficient.

OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT

2009 ◽  
Vol 18 (02) ◽  
pp. 311-323 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
MAJID MOHAMMADI ◽  
KEIVAN NAVI ◽  
MOHAMMAD ESHGHI
Keyword(s):  
Dna Computing ◽  
Full Adder ◽  
Logic Circuits ◽  
Optical Information ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Cmos Design ◽  
Fair Comparison ◽  
Low Power Cmos ◽  
Significant Attention

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Reliability Analysis of Repairable System With Multiple-Input and Multi-Function Component Based on Goal-Oriented Methodology

2016 ◽  
Vol 3 (1) ◽  
Author(s):  
Xiao-Jian Yi ◽  
Jian Shi ◽  
Hui-Na Mu ◽  
Hai-Ping Dong ◽  
Zhong Zhang
Keyword(s):  
Reliability Analysis ◽  
Fault Tree Analysis ◽  
Repairable Systems ◽  
New Approach ◽  
Availability Analysis ◽  
Analysis Process ◽  
Power Shift ◽  
Comparison Results ◽  
Multiple Input ◽  
First Time

This paper proposes a new goal-oriented (GO) method for reliability analysis of repairable systems with multiple-input and multi-function component (MIMFC). First, a new GO operator combination, which is composed of a new function GO operator and a new auxiliary GO operator, is created to represent MIMFC. The new function GO operator named as Type 22 operator is created to represent MIMFC itself, and the auxiliary GO operator named as Type 15B operator is created to represent multi-condition control signals of MIMFC. Then, GO operation formulas of the new GO operator combination are deduced based on logical relationships among inputs, outputs, and the component itself. The reliability analysis process of the new GO method is formulated. Furthermore, this new GO method is applied for the first time in steady availability analysis and qualitative analysis of the fan drive system of a power-shift steering transmission. Finally, the results obtained by the new GO method are compared with the results of fault tree analysis (FTA) and Monte Carlo simulation (MCS), and the comparison results show that this new GO method is reasonable and advantageous in reliability analysis of repairable systems with MIMFC. Moreover, the analysis process shows that it is more advantageous in the aspect of building system models and conducting reliability analysis. Overall, this paper not only improves the basic theory of the GO method and expands the application of the GO method, but it also provides a new approach for reliability analysis of repairable systems with MIMFC.

scholarly journals Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7
Author(s):  
Zhen-dong Zhang ◽  
Bin Wu ◽  
Yu-mei Zhou ◽  
Xin Zhang
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Complexity ◽  
Cmos Technology ◽  
Path Delay ◽  
Hardware Complexity ◽  
Ieee 802.11A ◽  
Comparison Results ◽  
Mathematical Formulas ◽  
High Flexibility

A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm2, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.

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