The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

2020 ◽  
Vol 12 (3) ◽  
pp. 146-148
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Arup K. Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Optimized Design ◽  
Quantum Cost ◽  
Constant Input ◽  
Logic Block ◽  
Reversible Gate ◽  
Garbage Output

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

2018 ◽  
Vol 16 (07) ◽  
pp. 1850061 ◽  
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Logic Gate ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Reversible Circuit ◽  
Reversible Gate ◽  
Garbage Output ◽  
Feynman Gate

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

2020 ◽  
Vol 12 ◽  
Author(s):  
Heranmoy Maity ◽  
Sudipta Banerjee ◽  
Raton Mistry ◽  
Parna Kundu ◽  
Kriti Ojha ◽  
...  
Keyword(s):  
Quantum Circuit ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Garbage Output ◽  
Feynman Gate ◽  
Cost Efficient ◽  
Optimized Code ◽  
Logic Functions ◽  
Very High

Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

2018 ◽  
Vol 16 (02) ◽  
pp. 1850016 ◽  
Author(s):  
H. Maity ◽  
A. Biswas ◽  
A. K. Bhattacharjee ◽  
A. Pal
Keyword(s):  
Quantum Computing ◽  
Logic Gate ◽  
Logic Gates ◽  
Reversible Logic ◽  
Shift Register ◽  
Optimized Design ◽  
Quantum Cost ◽  
Universal Shift Register ◽  
Reversible Logic Gates

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

2019 ◽  
Vol 17 (05) ◽  
pp. 1950048
Author(s):  
Abdollah Norouzi Doshanlou ◽  
Majid Haghparast ◽  
Mehdi Hosseinzadeh ◽  
Midia Reshadi
Keyword(s):  
System Performance ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Constant Input ◽  
Comparison Results ◽  
Garbage Output ◽  
First Time

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

1970 ◽  
Vol 32 (2) ◽  
Author(s):  
Md Saiful Islam ◽  
Zerina Begum
Keyword(s):  
Fault Tolerant ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Digital Signal ◽  
Full Adder ◽  
Research Area ◽  
Reversible Logic ◽  
Hardware Complexity ◽  
Fundamental Building Block ◽  
Reversible Gate

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts. Keywords: Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic. doi: 10.3329/jbas.v32i2.2431 Journal of Bangladesh Academy of Sciences Vol.32(2) 2008 234-250

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

scholarly journals Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module

2018 ◽  
Vol 7 (3.12) ◽  
pp. 808
Author(s):  
Srija Alla ◽  
Bharathi S H
Keyword(s):  
Power Dissipation ◽  
Vlsi Design ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Worst Case ◽  
Nano Technology ◽  
Flip Flop ◽  
Digital World ◽  
Reversible Gate ◽  
Cost Efficient

In the modern digital-world, power dissipation in microprocessors is becoming a significant challenge for the researchers to design an efficient reversible logic circuit. Thus, study on reversible logic design has been rapidly increased in present days for its application in Nano technology as well as in low energized VLSI design etc. In this current study, have realized a QC (i.e. quantum-cost) efficient (2i x j) reversible RAM array module with (3 x 3) New Modified Fredkin (NMF) reversible gate. Additionally, have introduced a Reversible D-Flip-Flop (RDFF) with less QC, and Reversible (i x 2i) decoder which produces the effective results in terms of QC and garbage-outputs. Finally, the study analyzed the designed architecture in terms of worst case delay.  

Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines

2013 ◽  
Vol 2 (1) ◽  
pp. 21
Author(s):  
P.Radhika Ramya ◽  
Y.Sudha Vani
Keyword(s):  
Energy Dissipation ◽  
Reversible Logic ◽  
Digital Design ◽  
General Idea ◽  
Minimal Energy ◽  
Toffoli Gate ◽  
Constant Input ◽  
Main Requirement ◽  
Garbage Output ◽  
Major Criterion

The Reversible logic plays an important role to obtain the minimal energy dissipation. It is the main requirement in the low power digital design. To implement a reversible function some additional lines are required. Sometimes it is more than the primary inputs which leads to increased size of the circuit. Hence the reducing the number of circuit lines is one of the major criterion in reversible logic. The general idea is to merge the garbage output lines with appropriate constant input lines. In this work, Toffoli gate implementation of BCD adder and press gate implementation of BCD adder is taken and an optimization algorithm has been applied to reduce the number of lines in the circuit. The kit used to implement the design is Vertex5 in which both the area and delay are analyzed.

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