Frequency dependence on polarization switching measurement in ferroelectric capacitors

Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges. Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous remnant polarization (P r) and coercive field (E c). In this study, positive-up-negative-down (PUND) measurement under a wide frequency range was performed on a 10-nm thick Hf0.5Zr0.5O2 ferroelectric film. Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor. After considering the time lag caused by RC delay, reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time. In such a method, rational P–V loops measured at high frequencies (>1 MHz) was successfully achieved. This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.

Positive-to-negative subthreshold swing of a MOSFET tuned by the ferroelectric switching dynamics of BiFeO3

Ferroelectricity can reduce the subthreshold swing (SS) of metal-oxide-semiconductor field-effect transistors (MOSFETs) to below the room-temperature Boltzmann limit of ~60 mV/dec and provides an important strategy to achieve a steeper SS. Surprisingly, by carefully tuning the polarization switching dynamics of BiFeO3 ferroelectric capacitors the SS of a commercial power MOSFET can even be tuned to zero or a negative value, i.e., the drain current increases with a constant or decreasing gate voltage. In particular, in addition to the positive SS of lower than 60 mV/dec, the zero and negative SS can be established with a drain current spanning for over seven orders of magnitude. These intriguing phenomena are explained by the ferroelectric polarization switching dynamics, which change the charge redistributions and accordingly affect the voltage drops across the ferroelectric capacitor and MOSFET. This study provides deep insights into understanding the steep SS in ferroelectric MOSFETs, which could be promising for designing advanced MOSFETs with an ultralow and tunable SS.