Packaging Challenges of Thin High Bandwidth POP

2019 ◽  
Author(s):  
Fletcher (Cheng-Piao) Tung ◽  
Jensen (Ying-Chou) Tsai ◽  
Yu-Po Wang ◽  
Joe (Chih-Nan) Lin ◽  
Gary (Yue-Long) Fan
Keyword(s):  
Printed Circuit Board ◽  
Lower Cost ◽  
Coefficient Of Thermal Expansion ◽  
Cellular Phone ◽  
Circuit Board ◽  
Printed Circuit ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Application Processor ◽  
Different Thickness

Abstract Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.

A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000887-000892 ◽  
Author(s):  
Rudi Hechfellner ◽  
Michiel Kruger ◽  
Tewe Heemstra ◽  
Greg Caswell ◽  
Nathan Blattau ◽  
...  
Keyword(s):  
Solder Joint ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Light Emitting Diodes ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Control ◽  
Circuit Board ◽  
System Level ◽  
Light Emitting ◽  
Printed Circuit

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance. The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime. In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models. It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..

Materials Characterization and Model of PCB Thermal Expansion for Laminates With Various Copper Densities and Thicknesses

2004 ◽  
Author(s):  
William J. Cunningham ◽  
Dick Casali ◽  
Norman J. Armendariz
Keyword(s):  
Thermal Expansion ◽  
Thermal Management ◽  
High Speed ◽  
Printed Circuit Board ◽  
Coefficient Of Thermal Expansion ◽  
Materials Characterization ◽  
Circuit Board ◽  
Printed Circuit ◽  
Printed Circuit Board Manufacturing ◽  
Increasing Temperature

Abstract The SEMATECH/SEMI roadmap forecasts increased density requirements for printed circuit board manufacturing to accommodate smaller form factor interconnects, increased pin counts, and routing densities on a range of PCB sizes and thicknesses. As a result, the effect of materials. thermal expansion properties may further impact the structural or physical integrity and subsequent electrical properties for high speed and thermal management requirements. This study demonstrated that various sample coupons selected from PCB boards with different amounts of copper showed a corresponding coefficient of thermal expansion (CTE) correlation in the Z-axis (CTEZ) and can be modeled using a constitutive equation. Moreover, samples were further evaluated from the effect of increasing temperature and showed that the CTE indeed affects copper-interconnect physical structures such as copper vias and barrels in terms of elongation or strain.

scholarly journals CHOOSING RATIONAL TRACING PROCEDURE BY CONSTRUCTIVE CRITERION

2019 ◽  
pp. 5-12
Author(s):  
Oleg Yu. Sisoev ◽  
Sergey S. Sokolov ◽  
Victor A. Tupik
Keyword(s):  
Integrated Circuits ◽  
Topological Space ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Mutual Influence ◽  
Buffer Zone ◽  
Circuit Board ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Fine Pitch

The analysis of autorouter efficiency in the known CAD systems under structural and technological constraints is carried out. The revealed significant constraints are related to the thermal strength of the wires and possible mutual influence through the electromagnetic field. When manually designing the designer guided by his own experience, can ignore these and other constraints. Unlike a person, the autorouter strictly fulfills all the specified constraints, which, given the topology of the printed circuit board, does not allow tracing to complete. On the other hand, giving greater freedom to the autorouter often makes it impossible to meet the production requirements on permissible parameters of the topological pat-tern, which is the width of the conductors and the gaps between them. The problem of tracing printed circuit boards, including multilayer ones, has become much more complicated with the introduction of integrated circuits in TSOP, MOFP and BGA type enclosures packages with fine-pitch pins, a number of which can reach several hundred. The article investigates the possibility of maximizing printed circuit board topological space with these and other types of enclosures. The necessity of introducing a buffer zone around the component to improve the routing efficiency is explained. It is shown, however, that the avail-ability of a buffer zone does not eliminate the appearance of vias in it, the number of which depends on the routing type. On the basis of the proposed criterion for the autorouter performance, i.e. the ratio of the total wire length to the number of vias, the efficiency of using the topological space of a printed circuit board by three autorouters is analyzed.The presented experimental results of competing routing systems TopoR and Specctra confirmed the possibility to enlarge the pattern area of the printed circuit board for its further use.

Sign in / Sign up

Export Citation Format

Share Document