scholarly journals FPGA Implementation of Fault Tolerant & High Speed Reversible Systolic Multiplier

2020 ◽  
pp. 537-542
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Logic Gates ◽  
Digital World ◽  
Essential Components ◽  
Static Power ◽  
Toffoli Gates ◽  
Reversible Logic Gates ◽  
Systolic Multiplier

Multiplier is one of the essential components in the digital world such as in digital signal processing, quantum computing, microprocessor and widely used in arithmetic unit. The Reversible rationale is a used to decrease heat scattering and data misfortune. Contrasted with all essential math activities, multiplication requests all the more preparing time and look for complex equipment. This paper presents a plan of low power Systolic Array Multiplier utilizing Reversible logic gates which performs information handling in parallel. In this paper, we present a high speed 4x4 Systolic Multiplier design by using peres gate and toffoli gates and source code written in verilog and also implemented on FPGA Spartan 3s50pq208-4. The synthesis and simulation is done on Xilinx ISE 14.7. The delay is 17.642ns and static power dissipation is 24mW.

scholarly journals Distillation protocols for Fourier states in quantum computing

2014 ◽  
Vol 14 (7&8) ◽  
pp. 560-576
Author(s):  
Cody Jones
Keyword(s):  
Signal Processing ◽  
Quantum Computing ◽  
Digital Signal Processing ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Arbitrary Phase ◽  
Toffoli Gates

Fourier states are multi-qubit registers that facilitate phase rotations in fault-tolerant quantum computing. We propose distillation protocols for constructing the fundamental, $n$-qubit Fourier state with error $O(2^{-n})$ at a cost of $O(n \log n)$ Toffoli gates and Clifford gates, or any arbitrary Fourier state using $O(n^2)$ gates. We analyze these protocols with methods from digital signal processing. These results suggest that phase kickback, which uses Fourier states, could be the current lowest-overhead method for generating arbitrary phase rotations.

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
S. Rasoul Faraji ◽  
Pierre Abillama ◽  
Kia Bazargan
Keyword(s):  
Discrete Cosine Transform ◽  
Video Processing ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Logic Gates ◽  
Cosine Transform ◽  
Real Time Processing ◽  
Coefficient Multiplier ◽  
Encoding Method

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals Design of High-Speed Multiplier Architecture Based on Vedic Mathematics

2018 ◽  
Vol 7 (2.4) ◽  
pp. 105
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran ◽  
Keerthana Prasad ◽  
V Siva Ramakrishna
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Expected Improvement ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Essential Components ◽  
Signal Processing Algorithms ◽  
Computational Circuits ◽  
Almost All

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

scholarly journals A review on reversible logic gates

2020 ◽  
Vol 12 (1) ◽  
pp. 242-250
Author(s):  
B.Y. Galadima ◽  
G.S.M. Galadanci ◽  
A. Tijjani ◽  
M. Ibrahim
Keyword(s):  
Digital Signal ◽  
Logic Gates ◽  
Propagation Delay ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Comparative Review ◽  
Reversible Logic Gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

scholarly journals ASIC design of low power-delay product carry pre-computation based multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 845
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Expected Improvement ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Essential Components ◽  
Computational Circuits ◽  
Power Delay Product ◽  
Almost All

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

scholarly journals Reversible Vedic Multiplier

2019 ◽  
Vol 8 (6S2) ◽  
pp. 852-857
Keyword(s):  
Embedded System ◽  
High Speed ◽  
Digital Signal ◽  
Design Parameters ◽  
Design Constraint ◽  
Performance Constraints ◽  
Multiplication Operation ◽  
Vedic Multiplier ◽  
Essential Components ◽  
Almost All

In the new era of technology speed effective advanced multiplier has greatest demand, where they acts as an essential part in almost all high speed processing units which are used currently. As the multiplier is one of the essential components in several computing machines, for instant microprocessors, DSPs (Digital Signal Processors) and quantum computational and combinational systems. The performances of different processors is measured based on number of multiplication completed per second. So efficient multiplier designs are to be found to meet these performance constraints and one such approach which provides solution to above problem is Vedic multiplier. It is simple in structure and increase the efficiency by reducing the unnecessary steps in multiplication. Furthermore, implementing the designed multiplier using reversible gates can decreases the dissipation of power also, which is another essential design constraint that to be met in an embedded system. In the present work, a 4X4 reversible Vedic multiplier is designed; moreover it can offers more efficiency in terms of reversible design parameters such as TRLIC (Total Reversible Logic Implementation Cost) and delay. Code for 4X4 Vedic multiplication operation is written using Verilog HDL programming language and simulation is done using Xilinx 14.7 ISE is targeted to selected FPGA device family as Vertex 6

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