Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Demonstration of on-chip gigahertz acousto-optic modulation at near-visible wavelengths

Lithium niobate integrated photonics has recently received significant attention because it exploits the attractive properties of lithium niobate on an integrated platform which provides strong optical confinement as well as high photonic integration density. Although many optical functionalities of lithium niobate have been demonstrated on a chip in the telecom band, the visible and near-visible regimes are less explored. This is mainly because devices with a relatively smaller feature size are required which increases fabrication difficulty. Here, we explored the acousto-optic effect of lithium niobate on a chip at near-visible wavelengths (765–781 nm) and demonstrated acousto-optic modulation with the modulation frequency up to 2.44 GHz. We adopted an etchless process for the device fabrication and applied the principle of bound states in the continuum to optimize the device performance. By demonstrating functionality at near-visible wavelengths, our devices will enable many on-chip applications ranging from frequency metrology to quantum information processing.

Failures in Soldering

Due to the recent requirement of higher integration density, solder joints are getting smaller in electronic product assemblies, which makes the joints more vulnerable to failure. Thus, the root-cause failure analysis for the solder joints becomes important to prevent failure at the assembly level. This article covers the properties of solder alloys and the corresponding intermetallic compounds. It includes the dominant failure modes introduced during the solder joint manufacturing process and in field-use applications. The corresponding failure mechanism and root-cause analysis are also presented. The article introduces several frequently used methods for solder joint failure detection, prevention, and isolation (identification for the failed location).

Measuring of an unknown voltage by using single electron transistor based voltmeter

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.

Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs

Quantum-dot cellular automata (QCA) technology is considered to be a possible alternative for circuit implementation in terms of energy efficiency, integration density and switching frequency. Multiplexer (MUX) can be considered to be a suitable candidate for designing QCA circuits. In this paper, two different structures of energy-efficient 2×1 MUX designs are proposed. These MUXes outperform the best existing design in terms of power consumption with approximate reductions of 26% and 35%. Moreover, similar or better performance factors such as area and latency are achieved compared to the available designs. These MUX structures can be used as fundamental energy-efficient building blocks for replacing the majority-based structures in QCA. The scalability property of the proposed MUXes is excellent and can be used for energy-efficient complex QCA circuit designs.

On optimization of manufacturing of a step-down DC-DC converter to increase integration density of elements

<p>We consider possibility to increase field-effect transistor's density in a switched-capacitor step-down DC-DC converter. Based on this approach we analyzed manufacturing of the converter in a heterostructure with special structure. Some specific sections of the heterostructure must be doped by ion implantation or by diffusion. After this procedure optimized annealing has been done. We also obtained conditions for decreasing of mismatch-induced stress value in this heterostructure. An analytical approach for analysis of heat and mass transport in multilayer structures has been introduced. The approach gives a possibility without crosslinking of solutionson interfaces between layers, take into account (i) spatial variation of parameters of considered processes; (ii) temporal variation of parameters of considered processes; (iii) nonlinearity of considered processes; (iv) mismatch-induced stress.</p>

Three-dimensional plasmonic nano-router via optical antennas

A three-dimensional (3D) nanoscale optical router is a much-desired component in 3D stacked optical integrated circuits. However, existing 3D routers based on dielectric configurations suffer from large footprints and nanoscale routers based on plasmonic antennas only work in a 2D in-plane scene. Here, we propose and experimentally demonstrate cross-layered all-optical 3D routers with nanoscale footprints. Optical slot antenna pairs are used to realize the routing of plasmonic signals between different layers for arbitrary direction in a broadband wavelength range. The routers are also integrated with waveguide directly for exploring further applications. Based on these router elements, a 3D network of optical butterfly interconnection is demonstrated for multi-directional all-optical data communication. The proposed configuration paves the way for optical cross-layer routing on the nanoscale and advances the research and applications for 3D plasmonic circuits with high integration density in the future.

Investigation on Thermal Resistance and Capacitance Characteristics of a Highly Integrated Power Control Unit Module

With the increasing integration density of power control unit (PCU) modules, more functional power converter units are integrated into a single module for applications in electric vehicles or hybrid electric vehicles (EVs/HEVs). Different types of power dies with different footprints are usually placed closely together. Due to the constraints from the placement of power dies and liquid cooling schemes, heat-flow paths from the junction to coolant are possibly inconsistent for power dies, resulting in different thermal resistance and capacitance (RC) characteristics of power dies. This presents a critical challenge for optimal liquid cooling at a low cost. In this paper, a highly integrated PCU module is developed for application in EVs/HEVs. The underlying mechanism of the inconsistent RC characteristics of power dies for the developed PCU module is revealed by experiments and simulations. It is found that the matching placement design of power dies with a heat sink structure and liquid cooler, as well as a liquid cooling scheme, can alleviate the inconsistent RC characteristics of power dies in highly integrated PCU modules. The findings in this paper provide valuable guidance for the design of highly integrated PCU modules.

Theoretical Analysis of Terahertz Dielectric–Loaded Graphene Waveguide

The waveguiding of terahertz surface plasmons by a GaAs strip-loaded graphene waveguide is investigated based on the effective-index method and the finite element method. Modal properties of the effective mode index, modal loss, and cut-off characteristics of higher order modes are investigated. By modulating the Fermi level, the modal properties of the fundamental mode could be adjusted. The accuracy of the effective-index method is verified by a comparison between the analytical results and numerical simulations. Besides the modal properties, the crosstalk between the adjacent waveguides, which determines the device integration density, is studied. The findings show that the effective-index method is highly valid for analyzing dielectric-loaded graphene plasmon waveguides in the terahertz region and may have potential applications in subwavelength tunable integrated photonic devices.