Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

2022 ◽  
Vol 18 (1) ◽  
pp. 1-37
Author(s):  
Arjun Chaudhuri ◽  
Sanmitra Banerjee ◽  
Jinwoo Kim ◽  
Heechun Park ◽  
Bon Woong Ku ◽  
...  
Keyword(s):  
Low Cost ◽  
Multiple Faults ◽  
Integration Density ◽  
Small Delay ◽  
Block Level ◽  
Self Test ◽  
Fault Masking ◽  
Built In Self Test ◽  
Delay Defects ◽  
The Impact

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

A low-cost built-in self-test method for thermally actuated resistive MEMS sensors

2013 ◽  
Vol 194 ◽  
pp. 8-15 ◽  
Author(s):  
O. Legendre ◽  
H. Bertin ◽  
H. Mathias ◽  
S. Megherbi ◽  
J. Juillard ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Method ◽  
Mems Sensors ◽  
Self Test ◽  
Built In Self Test ◽  
Thermally Actuated

scholarly journals Real-Time Built-In Self-Test of MEMS Gyroscope Based on Quadrature Error Signal

Micromachines ◽  
2021 ◽  
Vol 12 (9) ◽  
pp. 1115
Author(s):  
Rui Feng ◽  
Jiong Wang ◽  
Wei Qiao ◽  
Fu Wang ◽  
Ming Zhou ◽  
...  
Keyword(s):  
Real Time ◽  
Output Signal ◽  
High Reliability ◽  
Scale Factor ◽  
Error Signal ◽  
Mems Gyroscope ◽  
Quadrature Error ◽  
Self Test ◽  
Built In Self Test ◽  
The Impact

In high-reliability applications, the health condition of the MEMS gyroscope needs to be known in real time to ensure that the system does not fail due to the wrong output signal. Because the MEMS gyroscope self-test based on the principle of electrostatic force cannot be performed during the working state. We propose that by monitoring the quadrature error signal of the MEMS gyroscope in real time, an online self-test of the MEMS gyroscope can be realized. The correlation between the gyroscope’s quadrature error amplitude signal and the gyroscope scale factor and bias was theoretically analyzed. Based on the sixteen-sided cobweb-like MEMS gyroscope, the real-time built-in self-test (BIST) method of the MEMS gyroscope based on the quadrature error signal was verified. By artificially setting the control signal of the gyroscope to zero, we imitated several scenarios where the gyroscope malfunctioned. Moreover, a mechanical impact table was used to impact the gyroscope. After a 6000 g shock, the gyroscope scale factor, bias, and quadrature error amplitude changed by −1.02%, −5.76%, and −3.74%, respectively, compared to before the impact. The gyroscope failed after a 10,000 g impact, and the quadrature error amplitude changed −99.82% compared to before the impact. The experimental results show that, when the amplitude of the quadrature error signal seriously deviates from the original value, it can be determined that the gyroscope output signal is invalid.

scholarly journals Design of a Realistic Test Simulator For a Built-In Self Test Environment

2010 ◽  
Vol 7 (2) ◽  
pp. 69 ◽  
Author(s):  
A. Ahmad ◽  
D. Al-Abri
Keyword(s):  
Fault Tolerant ◽  
Low Cost ◽  
Bench Mark ◽  
Test Environment ◽  
Digital Electronics ◽  
Special Software ◽  
Programming Skill ◽  
Self Test ◽  
Built In Self Test ◽  
Fault Grading

 This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs. 

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