Reconfigurable structure and tunable transport in synchronized active spinner materials

Ensembles of actuated colloids are excellent model systems to explore emergent out-of-equilibrium structures, complex collective dynamics, and design rules for the next generation materials. Here, we demonstrate that ferromagnetic microparticles suspended at an air-water interface and energized by an external rotating magnetic field spontaneously form dynamic ensembles of synchronized spinners in a certain range of the excitation field parameters. Each spinner generates strong hydrodynamic flows, and collective interactions of the multiple spinners promote a formation of dynamic lattices. On the basis of experiments and simulations, we reveal structural transitions from liquid to nearly crystalline states in this novel active spinner material and demonstrate that dynamic spinner lattices are reconfigurable, capable of self-healing behavior and that the transport of embedded inert cargo particles can be remotely tuned by the parameters of the external excitation field. Our findings provide insights into the behavior of active spinner materials with reconfigurable structural order and tunable functionalities.

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

Power consumption, earlier a design constraint only in embedded systems, has become the major driver for architectural optimizations in all domains, from the cloud to the edge. Application-specific accelerators provide a low-power processing solution by efficiently matching the hardware to the application; however, since in many domains the hardware must execute efficiently a broad range of fast-evolving applications, unpredictable at design time and each with distinct resource requirements, alternatives approaches are required. Besides that, the same hardware must also adapt the computational power at run time to the system status and workload sizes. To address these issues, this thesis presents a general-purpose reconfigurable accelerator that can be coupled to a heterogeneous set of cores and supports Dynamic Voltage and Frequency Scaling (DVFS), synergistically combining the techniques for a better match between different applications and hardware when compared to current designs. The resulting architecture, MuTARe, provides a coarse-grained regular and reconfigurable structure which is suitable for automatic acceleration of deployed code through dynamic binary translation. In extension to that, the structure of MuTARe is further leveraged to apply two emerging computing paradigms that can boost the power-efficiency: Near-Threshold Voltage (NTV) computing (while still supporting transparent acceleration) and Approximate Computing (AxC). Compared to a traditional heterogeneous system with DVFS support, the base MuTARe architecture can automatically improve the execution time by up to 1:3×, or adapt to the same task deadline with 1:6× smaller energy consumption, or adapt to the same low energy budget with 2:3× better performance. In NTV mode, MuTARe can transparently save further 30% energy in memory-intensive workloads by operating the combinatorial datapath at half the memory frequency. In AxC mode, MuTARe can further improve power savings by up to 50% by leveraging approximate functional units for arithmetic computations.

A Novel CMOS CCCII with Wide Tunable Rx and Its Application

This paper introduces a novel CMOS second-generation current-controlled current conveyor (CCCII) that has a wide tunable intrinsic resistance ([Formula: see text]. The designed structure is achieved by the combination of one ordinary CCCII, one cross-coupled OTA and one active resistor. An inverse relationship between the intrinsic resistance and external bias current is created for the first time in CMOS CCCII design, which results in wide tuning range of [Formula: see text]. Performance of the proposed circuit is discussed by detailed analysis. The CMOS CCCII is simulated in TSMC 0.18[Formula: see text][Formula: see text]m RF CMOS technology. The simulation results confirm that the proposed CMOS CCCII achieves a wide tunable [Formula: see text] (from 197.4[Formula: see text][Formula: see text] to 27.23[Formula: see text]k[Formula: see text]) while maintaining favorable performance in bandwidth, transfer gain and linear range. In addition, a new reconfigurable structure, which can function as a universal filter or a quadrature oscillator via controlling an enabled switch, is given as an application example to validate the feasibility of the proposed CMOS CCCII.