scholarly journals High‐performance SIMD modular arithmetic for polynomial evaluation

2021 ◽  
Author(s):  
Pierre Fortin ◽  
Ambroise Fleury ◽  
François Lemaire ◽  
Michael Monagan
Keyword(s):  
High Performance ◽  
Modular Arithmetic ◽  
Polynomial Evaluation

scholarly journals Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF(p)

2007 ◽  
Vol 94 (5) ◽  
pp. 501-514 ◽  
Author(s):  
K. Sakiyama ◽  
N. Mentens ◽  
L. Batina ◽  
B. Preneel ◽  
I. Verbauwhede
Keyword(s):  
High Performance ◽  
Modular Arithmetic ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals SIDH on ARM: Faster Modular Multiplications for Faster Post-Quantum Supersingular Isogeny Key Exchange

2018 ◽  
pp. 1-20 ◽  
Author(s):  
Hwajeong Seo ◽  
Zhe Liu ◽  
Patrick Longa ◽  
Zhi Hu
Keyword(s):  
High Speed ◽  
High Performance ◽  
Key Exchange ◽  
Modular Arithmetic ◽  
Diffie Hellman ◽  
Real World Applications ◽  
Diffie Hellman Key Exchange ◽  
Memory Accesses ◽  
Montgomery Reduction ◽  
Cache Attacks

We present high-speed implementations of the post-quantum supersingular isogeny Diffie-Hellman key exchange (SIDH) and the supersingular isogeny key encapsulation (SIKE) protocols for 32-bit ARMv7-A processors with NEON support. The high performance of our implementations is mainly due to carefully optimized multiprecision and modular arithmetic that finely integrates both ARM and NEON instructions in order to reduce the number of pipeline stalls and memory accesses, and a new Montgomery reduction technique that combines the use of the UMAAL instruction with a variant of the hybrid-scanning approach. In addition, we present efficient implementations of SIDH and SIKE for 64-bit ARMv8-A processors, based on a high-speed Montgomery multiplication that leverages the power of 64-bit instructions. Our experimental results consolidate the practicality of supersingular isogeny-based protocols for many real-world applications. For example, a full key-exchange execution of SIDHp503 is performed in about 176 million cycles on an ARM Cortex-A15 from the ARMv7-A family (i.e., 88 milliseconds @2.0GHz). On an ARM Cortex-A72 from the ARMv8-A family, the same operation can be carried out in about 90 million cycles (i.e., 45 milliseconds @1.992GHz). All our software is protected against timing and cache attacks. The techniques for modular multiplication presented in this work have broad applications to other cryptographic schemes.

Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems

2020 ◽  
Vol 29 (13) ◽  
pp. 2050214
Author(s):  
S. Elango ◽  
P. Sampath
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Modular Arithmetic ◽  
Data Path ◽  
Verilog Hdl ◽  
Vlsi Architectures ◽  
Field Programmable ◽  
Parallel Prefix ◽  
Mathematical Equations ◽  
Power Delay Product

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.

A High Performance Energy Analyzer for Use in Electron Scanning Microscopy

1969 ◽  
Vol 27 ◽  
pp. 14-15
Author(s):  
A. V. Crewe ◽  
M. Isaacson ◽  
D. Johnson
Keyword(s):  
High Performance ◽  
Vertical Plane ◽  
Median Plane ◽  
Electron Gun ◽  
Uniform Field ◽  
Loss Mechanism ◽  
Electron Scanning Microscopy ◽  
Sector Type ◽  
Double Focusing ◽  
Electron Energy Loss

A double focusing magnetic spectrometer has been constructed for use with a field emission electron gun scanning microscope in order to study the electron energy loss mechanism in thin specimens. It is of the uniform field sector type with curved pole pieces. The shape of the pole pieces is determined by requiring that all particles be focused to a point at the image slit (point 1). The resultant shape gives perfect focusing in the median plane (Fig. 1) and first order focusing in the vertical plane (Fig. 2).

Vacuum System to Minimize the Specimen Contamination of High-Performance EM

1977 ◽  
Vol 35 ◽  
pp. 68-69
Author(s):  
N. Yoshimura ◽  
K. Shirota ◽  
T. Etoh
Keyword(s):  
Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Vacuum System ◽  
Pump System ◽  
Pumping System ◽  
Diffusion Pump ◽  
Almost All ◽  
Cascade Type

One of the most important requirements for a high-performance EM, especially an analytical EM using a fine beam probe, is to prevent specimen contamination by providing a clean high vacuum in the vicinity of the specimen. However, in almost all commercial EMs, the pressure in the vicinity of the specimen under observation is usually more than ten times higher than the pressure measured at the punping line. The EM column inevitably requires the use of greased Viton O-rings for fine movement, and specimens and films need to be exchanged frequently and several attachments may also be exchanged. For these reasons, a high speed pumping system, as well as a clean vacuum system, is now required. A newly developed electron microscope, the JEM-100CX features clean high vacuum in the vicinity of the specimen, realized by the use of a CASCADE type diffusion pump system which has been essentially improved over its predeces- sorD employed on the JEM-100C.

Use of the Magnetostatic Analogue In Electromagnetic Lens Engineering

1970 ◽  
Vol 28 ◽  
pp. 360-361
Author(s):  
John W. Coleman
Keyword(s):  
Boundary Conditions ◽  
High Performance ◽  
Force Fields ◽  
Optical Design ◽  
Direct Conversion ◽  
Design Engineering ◽  
Design Data ◽  
Scalar Potentials ◽  
Geometric Elements ◽  
At Will

In the design engineering of high performance electromagnetic lenses, the direct conversion of electron optical design data into drawings for reliable hardware is oftentimes difficult, especially in terms of how to mount parts to each other, how to tolerance dimensions, and how to specify finishes. An answer to this is in the use of magnetostatic analytics, corresponding to boundary conditions for the optical design. With such models, the magnetostatic force on a test pole along the axis may be examined, and in this way one may obtain priority listings for holding dimensions, relieving stresses, etc..The development of magnetostatic models most easily proceeds from the derivation of scalar potentials of separate geometric elements. These potentials can then be conbined at will because of the superposition characteristic of conservative force fields.

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