Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems

2020 ◽  
Vol 29 (13) ◽  
pp. 2050214
Author(s):  
S. Elango ◽  
P. Sampath
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Modular Arithmetic ◽  
Data Path ◽  
Verilog Hdl ◽  
Vlsi Architectures ◽  
Field Programmable ◽  
Parallel Prefix ◽  
Mathematical Equations ◽  
Power Delay Product

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.

A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy
Keyword(s):  
Video Processing ◽  
Power Dissipation ◽  
Field Programmable Gate Array ◽  
Video Codec ◽  
Floating Point ◽  
Data Path ◽  
Image And Video Processing ◽  
Field Programmable ◽  
Minimum Number ◽  
Code Language

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

Field Programmable Gate Array (FPGA) Based Microwave Oven

2019 ◽  
Vol 892 ◽  
pp. 120-126
Author(s):  
Thangavel Bhuvaneswari ◽  
Nor Hidayati Abdul Aziz ◽  
Jakir Hossen ◽  
Chinthakunta Venkataseshaiah
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Controller Design ◽  
Microwave Oven ◽  
High Potential ◽  
Verilog Hdl ◽  
Quartus Ii ◽  
Field Programmable ◽  
Real Time Applications ◽  
Simulation Results

In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Photon Correlator Implemented by Field Programmable Gate Array

2014 ◽  
Vol 513-517 ◽  
pp. 4171-4174
Author(s):  
Xing Guang Qi ◽  
Yan Min Zhang ◽  
Qing Hua Li ◽  
Ning Wang
Keyword(s):  
Software Design ◽  
Field Programmable Gate Array ◽  
Photon Correlation Spectroscopy ◽  
Correlation Spectroscopy ◽  
Correlation Technique ◽  
Good Prospect ◽  
Verilog Hdl ◽  
Photon Correlation ◽  
Field Programmable ◽  
Spectroscopy Experiment

Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This technology has a good prospect and commercial value. Photon correlator is used in photon correlation spectroscopy experiment to gain the photon correlation function. In order to obtain the accurate values of the photon correlation, efficient and accurate photon correlator must be designed. This paper presents one kind of photon correlator implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in the integration circumstance of ISE. The photon correlator can meet the different requirements of photon correlation.

Sign in / Sign up

Export Citation Format

Share Document