Survey of integrated-circuit-oscillator phase-noise analysis

2013 ◽  
Vol 42 (9) ◽  
pp. 871-938 ◽  
Author(s):  
Erik Pankratz ◽  
Edgar Sánchez-Sinencio
2010 ◽  
Vol 2 (1) ◽  
pp. 54-58
Author(s):  
Jevgenij Charlamov

In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.


2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method


Sign in / Sign up

Export Citation Format

Share Document