A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process

2014 ◽  
Vol 43 (7) ◽  
pp. 929-943 ◽  
Author(s):  
Soolmaz Abbasalizadeh ◽  
Samad Sheikhaei ◽  
Behjat Forouzandeh

Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.



2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Tanya Vanessa Abaya ◽  
Frederick Ray I. Gomez

The paper presents a design of a two-stage fully-differential operational transconductance amplifier (OTA) for a 10-bit 40-Msamples/s Nyquist rate analog-to-digital converter (ADC) using  a standard 0.35µm complementary metal-oxide semiconductor (CMOS) process.  A telescopic cascode topology is implemented as main stage, with common source amplifiers as output stage for the differential outputs. The open loop amplifier achieved a gain of 108dB, while the closed loop gain is at 12dB with settling time of less than 11ns for an accuracy of 0.5%.  Total output noise achieved is 63.4uVrms.  Loop unity gain bandwidth is 205MHz with phase margin of 77.6°. The design has a dynamic range of 88.3dB, and power consumption of 26.6mW from a 3V supply.



Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 612
Author(s):  
Gianluca Giustolisi ◽  
Gaetano Palumbo

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.





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