scholarly journals Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 612
Author(s):  
Gianluca Giustolisi ◽  
Gaetano Palumbo
Keyword(s):  
Design Strategy ◽  
Settling Time ◽  
Step Response ◽  
Cmos Process ◽  
Efficient Design ◽  
Operational Transconductance Amplifier ◽  
Large Signal ◽  
Transconductance Amplifier ◽  
Rate Effects ◽  
Analytical Criterion

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process

2014 ◽  
Vol 43 (7) ◽  
pp. 929-943 ◽  
Author(s):  
Soolmaz Abbasalizadeh ◽  
Samad Sheikhaei ◽  
Behjat Forouzandeh
Keyword(s):  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

scholarly journals Design of Two-Stage Fully-Differential Operational Transconductance Amplifier Using a Standard 0.35µm CMOS Process

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Tanya Vanessa Abaya ◽  
Frederick Ray I. Gomez
Keyword(s):  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Total Output ◽  
Common Source ◽  
Cmos Process ◽  
Main Stage ◽  
Operational Transconductance Amplifier ◽  
Two Stage ◽  
Fully Differential ◽  
Transconductance Amplifier

The paper presents a design of a two-stage fully-differential operational transconductance amplifier (OTA) for a 10-bit 40-Msamples/s Nyquist rate analog-to-digital converter (ADC) using  a standard 0.35µm complementary metal-oxide semiconductor (CMOS) process.  A telescopic cascode topology is implemented as main stage, with common source amplifiers as output stage for the differential outputs. The open loop amplifier achieved a gain of 108dB, while the closed loop gain is at 12dB with settling time of less than 11ns for an accuracy of 0.5%.  Total output noise achieved is 63.4uVrms.  Loop unity gain bandwidth is 205MHz with phase margin of 77.6°. The design has a dynamic range of 88.3dB, and power consumption of 26.6mW from a 3V supply.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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