Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique

2021 ◽  
Author(s):  
Roowz Saini ◽  
Kulbhushan Sharma ◽  
Rajnish Sharma
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
High Gain ◽  
Low Noise ◽  
Operational Transconductance Amplifier ◽  
Sensor Applications ◽  
Transconductance Amplifier ◽  
Folded Cascode

Operational Transconductance Amplifier (OTA) is an important circuit block used in the design of filter, amplifiers and oscillators for various analog-mixed circuit systems. However, design of a low-noise, high-gain OTA with low-power consumption is a challenging task in CMOS technology owing to high-power requirements of OTA for emulating high gain. This paper represents the design of gate-driven quasi-floating bulk recycling folded cascode (GDQFB RFC) OTA which has been shown to provide low-noise operation, emulates high gain and draws very less power. The design utilizes the gate-driven quasi-floating bulk (GDQFB) technique on a recycling folded cascode structure, which enhances the transconductance of OTA and improves its performance. All the post-layout simulation results have been obtained in 0.18-[Formula: see text]m CMOS N-well technology using BSIM3V3 device models. The obtained results indicate very high gain of 100.4 dB, gain-bandwidth of 69[Formula: see text]kHz, phase margin of 51.9∘ with power consumption of 2.31[Formula: see text][Formula: see text]W from [Formula: see text][Formula: see text]V supply voltage. The input referred noise emulated by proposed OTA is 0.684, 0.21 and 0.0592[Formula: see text][Formula: see text]V/[Formula: see text]Hz @ 1[Formula: see text]Hz, 10[Formula: see text]Hz and 1[Formula: see text]kHz, respectively. The input common mode range and output voltage swing are found to be [Formula: see text] to 0.669[Formula: see text]V and [Formula: see text] to 0.610[Formula: see text]V, respectively. Corner simulations and Monte Carlo analysis have been performed to verify the robustness of the proposed OTA. The proposed OTA can be used in design of filters and amplifiers for bio-instruments, sensor applications, neural recording applications and human implants etc.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950192
Author(s):  
Zhe Li ◽  
Rui Ma ◽  
Maliang Liu ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Model Stability ◽  
Analysis And Design ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Compensation Technique ◽  
Layout Area ◽  
The Stability

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [Formula: see text]-[Formula: see text] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[Formula: see text]nm 1.2[Formula: see text]V CMOS process, achieving 808[Formula: see text]MHz gain-bandwidth, 119[Formula: see text]dB DC gain, 585[Formula: see text]V/[Formula: see text]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[Formula: see text]V with power consumption of 2.17[Formula: see text]mW and the layout area is 0.011[Formula: see text]mm2.

Design of High Gain CMOS Folded Cascode Operational Amplifier

2013 ◽  
Vol 389 ◽  
pp. 573-578
Author(s):  
Ming Xin Song ◽  
Yue Li ◽  
Meng Meng Xu
Keyword(s):  
Power Supply ◽  
Operational Amplifier ◽  
High Gain ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Input Stage ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

scholarly journals 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

2021 ◽  
Vol 11 (4) ◽  
pp. 37
Author(s):  
Andrea Ballo ◽  
Salvatore Pennisi ◽  
Giuseppe Scotti
Keyword(s):  
Supply Voltage ◽  
Current Control ◽  
Cmos Inverter ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Quiescent Current ◽  
Bulk Technology ◽  
Inverter Topology

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

scholarly journals Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Ziad Alsibai ◽  
Salma Bay Abo Dabbous
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bias Current ◽  
Floating Gate ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

2019 ◽  
Vol 15 (4) ◽  
pp. 379-387
Author(s):  
Tayebeh Asiyabi ◽  
Jafar Torfifard
Keyword(s):  
Power Dissipation ◽  
State Of The Art ◽  
Operational Transconductance Amplifier ◽  
Power Efficient ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Multistage Amplifiers ◽  
Dc Gain ◽  
Capacitive Load ◽  
Unity Gain

In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

scholarly journals FIN-FET BASED HIGH GAIN OP-AMP WITH SLEW RATE ENHANCEMENT IN 45-NM REGIME

2020 ◽  
Vol 6 (7) ◽  
pp. 27-33
Author(s):  
Nagendra Tiwari ◽  
Bharati Chourasia
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Silicon On Insulator ◽  
Slew Rate ◽  
Video Signals ◽  
Op Amp ◽  
Dynamic Biasing ◽  
Unity Gain ◽  
Two Stages

In this paper dynamic biasing technique is used for the enhancing the slew rate of the designed Op-Amp. The proposed FinFET based Op-Amp has been verified through Hspice simulator in the standard 45nm Silicon on Insulator FinFET library. The proposed op amp has two stages Miller compensated configuration. A biasing circuit (DSB circuit) is used for dynamic switching of the biasing voltage of the op amp. This leads to lower power consumption, wide ICMR range, and high gain stability. The proposed op amp has a power consumption of 661.83 μW. It has a dual supply voltage of -1.0V and 1.0V. The input common mode range (ICMR) is -800 mV to +900 mV. The Op-Amp has a slew rate of 1.5 KV/μs. Voltage gain of the op amp is 90.4dB. Due to the use of SOI FINFET devices the op amp has relatively less leakage current as compared to similar bulk MOSFET device op amps. The op amp has unity gain bandwidth of 1.27 GHz. Thus, it can be used to transmission and processing of audio and video signals.

Design of Wide Bandwidth, High-CMRR Voltage and Transadmittance-Mode Instrumentation Amplifier Using a Single CBTA

2019 ◽  
Vol 29 (04) ◽  
pp. 2050060
Author(s):  
Mehmet Sagbas ◽  
Umut Engin Ayten
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
High Gain ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Wide Bandwidth ◽  
Current Output ◽  
Transconductance Amplifier ◽  
Low Offset ◽  
Electronically Tunable

In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18[Formula: see text][Formula: see text]m CMOS process with [Formula: see text][Formula: see text]V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs

2015 ◽  
Vol 24 (07) ◽  
pp. 1550104 ◽  
Author(s):  
Sarang Kazeminia ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Fast Response ◽  
Design Flow ◽  
Ring Oscillator ◽  
Operating Frequency ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Loop Filter ◽  
Wide Range

A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6–4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.

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