P.8: Trap States in Amorphous In-Sn-Zn-O Thin-Film Transistors Analyzed Using Dependence on Channel Thickness

InSnO (ITO) thin-film transistors (TFTs) attract much attention in fields of displays and low-cost integrated circuits (IC). In the present work, we demonstrate the high-performance, robust ITO TFTs that fabricated at process temperature no higher than 100 °C. The influences of channel thickness (tITO, respectively, 6, 9, 12, and 15 nm) on device performance and positive bias stress (PBS) stability of the ITO TFTs are examined. We found that content of oxygen defects positively correlates with tITO, leading to increases of both trap states as well as carrier concentration and synthetically determining electrical properties of the ITO TFTs. Interestingly, the ITO TFTs with a tITO of 9 nm exhibit the best performance and PBS stability, and typical electrical properties include a field-effect mobility (µFE) of 37.69 cm2/Vs, a Von of −2.3 V, a SS of 167.49 mV/decade, and an on–off current ratio over 107. This work paves the way for practical application of the ITO TFTs.

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Evaluation of grain boundary trap states in polycrystalline–silicon thin-film transistors by mobility and capacitance measurements

Journal of Applied Physics ◽

10.1063/1.1454202 ◽

2002 ◽

Vol 91 (7) ◽

pp. 4637-4645 ◽

Cited By ~ 46

Author(s):

H. Ikeda

Keyword(s):

Thin Film ◽

Grain Boundary ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Trap States ◽

Silicon Thin Film ◽

Capacitance Measurements

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An analytical modeling approach to the electrical behavior of the bottom-contact organic thin-film transistors in presence of the trap states

Journal of Computational Electronics ◽

10.1007/s10825-019-01314-6 ◽

2019 ◽

Vol 18 (2) ◽

pp. 543-552 ◽

Cited By ~ 2

Author(s):

Farkhanda Ana ◽

Najeeb-ud-Din

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Analytical Modeling ◽

Organic Thin Film Transistors ◽

Trap States ◽

Organic Thin Film ◽

Electrical Behavior ◽

Modeling Approach ◽

Bottom Contact

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Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin-film transistors

Electronics and Communications in Japan (Part II Electronics) ◽

10.1002/ecjb.20124 ◽

2005 ◽

Vol 88 (2) ◽

pp. 1-10 ◽

Cited By ~ 2

Author(s):

Mutsumi Kimura

Keyword(s):

Thin Film ◽

Grain Boundaries ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Electrical Characteristic ◽

Device Simulation ◽

Trap States ◽

Characteristic Analysis ◽

Silicon Thin Film ◽

Oxide Interfaces

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Pentacene Thin-film Transistors Fabricated with a Simple Solution Process

MRS Proceedings ◽

10.1557/proc-0937-m10-32 ◽

2006 ◽

Vol 937 ◽

Cited By ~ 1

Author(s):

Yutaka Natsume ◽

Takashi Minakata

Keyword(s):

Thin Film ◽

Thin Films ◽

Thin Film Transistors ◽

Carrier Mobility ◽

Solution Process ◽

Simple Solution ◽

Trap States ◽

Solution Processed ◽

High Crystallinity ◽

Transfer Characteristics

ABSTRACTWe have succeeded in developing a simple solution process of pentacene thin films without particular precursor materials. High crystallinity and large plate-like grains of the solution-processed thin films were observed with several analyses. The solution-processed pentacene thin-film transistors (TFTs) were also fabricated and exhibited good transfer characteristics with maximum carrier mobility above 1 cm2/Vs. The solution-processed TFTs also indicated a steep subthreshold swing and high stability of the threshold voltage against the storage in the atmosphere. The trap states and the bulk carrier density in the films were evaluated from the transfer characteristics by using the analytical model. We considered that these good properties could be attributed to the high crystallinity and the large grains of the solution-processed thin films.

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