A Low-Voltage 5.8-GHz Complementary Metal Oxide Semiconductor Transceiver Front-End Chip Design for Dedicated Short-Range Communication Application

2013 ◽  
pp. 1035-1043
Author(s):  
Jhin-Fang Huang ◽  
Jiun-Yu Wen ◽  
Yong-Jhen Jiangn
Keyword(s):  
Metal Oxide ◽  
Short Range ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Chip Design ◽  
Dedicated Short Range Communication ◽  
Front End

Complementary metal oxide semiconductor compatible high-voltage transistors

1987 ◽  
Vol 65 (8) ◽  
pp. 1003-1008
Author(s):  
P. Kempf ◽  
R. Hadaway ◽  
J. Kolk
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Process Model ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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