New Solutions for Cross-Layer System-Level and High-Level Synthesis

2017 ◽  
pp. 103-134
Author(s):  
Wei Zuo ◽  
Swathi Gurumani ◽  
Kyle Rupnow ◽  
Deming Chen
Keyword(s):  
System Level ◽  
High Level Synthesis ◽  
Cross Layer ◽  
Layer System ◽  
High Level

New solutions for system-level and high-level synthesis (Invited paper)

2014 ◽  
Author(s):  
Wei Zuo ◽  
Hongbin Zheng ◽  
Swathi T. Guruman ◽  
Kyle Rupnow ◽  
Deming Chen
Keyword(s):  
System Level ◽  
High Level Synthesis ◽  
High Level

scholarly journals High level synthesis design flow for multi parametric optimization with hybrid hierarchical design space exploration

2021 ◽  
Author(s):  
Zhipeng Zeng
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Design Flow ◽  
System Level ◽  
High Level Synthesis ◽  
Efficient Design ◽  
Optimum Result ◽  
Fuzzy Search ◽  
High Level

High Level Synthesis (HLS) has definitely bridged the pathway between the Electronic System Level (ESL) and its respective structural block at the Register Transfer Level (RTL). However, the most critical task during HLS is to assess and find a superior architecture from the design space that meets the design objectives. This thesis introduces a novel mechanism for efficient Design Space Exploration (DSE) based on Priority Facgtor using the Fuzzy search technique to achieve the optimum result. This novel approach is more efficient than traditional DSE approaches and is capable of drastically reducing the number of architectural variants to be assessed for architecture selection. The proposed method, when applied to a number of benchmarks, yielded improved results with remarkable speedup compared to the existing approach. The HLS design flow shown in this thesis uses the proposed approach for DSE with optimization of three parameters, hardware area, execution time and power consumption.

scholarly journals High level synthesis design flow for multi parametric optimization with hybrid hierarchical design space exploration

2021 ◽  
Author(s):  
Zhipeng Zeng
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Design Flow ◽  
System Level ◽  
High Level Synthesis ◽  
Efficient Design ◽  
Optimum Result ◽  
Fuzzy Search ◽  
High Level

High Level Synthesis (HLS) has definitely bridged the pathway between the Electronic System Level (ESL) and its respective structural block at the Register Transfer Level (RTL). However, the most critical task during HLS is to assess and find a superior architecture from the design space that meets the design objectives. This thesis introduces a novel mechanism for efficient Design Space Exploration (DSE) based on Priority Facgtor using the Fuzzy search technique to achieve the optimum result. This novel approach is more efficient than traditional DSE approaches and is capable of drastically reducing the number of architectural variants to be assessed for architecture selection. The proposed method, when applied to a number of benchmarks, yielded improved results with remarkable speedup compared to the existing approach. The HLS design flow shown in this thesis uses the proposed approach for DSE with optimization of three parameters, hardware area, execution time and power consumption.

scholarly journals A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA

2020 ◽  
Vol 12 (3) ◽  
pp. 80-84
Author(s):  
Syed Jahanzeb Hussain Pirzada ◽  
◽  
Abid Murtaza ◽  
Tongge Xu ◽  
Liu Jianwei
Keyword(s):  
Rapid Prototyping ◽  
Hardware Implementation ◽  
Digital Systems ◽  
System Level ◽  
High Level Synthesis ◽  
Time To Market ◽  
Model Based ◽  
Stage Of Development ◽  
Trade Offs ◽  
High Level

The digital design methodologies are evolving with the increase of digital systems utilization in daily life. The Model Based Design (MBD) methodology provides a unique methodology for design and implementation of digital systems on Field Programmable Gate Array (FPGA). Recently, a lot of research effort has been put to exploit new methodologies for designing and prototyping of digital systems on FPGA. The FPGA hardware provides prototyping which provides means of verifying your design at an early stage of development cycle. This helps to evaluate design trade-offs by testing the design in real-time on hardware. Making prototypes is a common practice in research-oriented projects. However, it requires excess development time which increases time to market of the product. This paper illustrates the use of reconfigurable MBD for rapid prototyping of digital systems on Microsemi ACTEL FPGAs for improving the design-cycle and time-to-market of a product. The model is simulated to verify the functionality of the design at system-level and a high-level code is generated from the MBD toolset embedded in MATLAB for hardware implementation. Then, a High-Level Synthesis (HLS) is performed on the generated code which converts this high-level code into Verilog-HDL suitable for hardware implementation on FPGA. Hence, this work presents a methodology and its analysis for design of digital system using high-level synthesis on Microsemi ACTEL FPGA.

scholarly journals Are HLS Tools Healthy? The C-Cubed Project

2015 ◽  
Vol 5 (2) ◽  
pp. 790-794
Author(s):  
M. Dossis ◽  
G. Dimitriou
Keyword(s):  
Integrated Circuits ◽  
Systems Engineering ◽  
Critical Role ◽  
Formal System ◽  
Electronic System ◽  
System Level ◽  
High Level Synthesis ◽  
Practical Reasons ◽  
Engineering Practice ◽  
High Level

The increasing complexity of Application Specific Integrated Circuits (ASICs) and Systems-on-Chip (SoCs) that incorporate custom and standard embedded core IP blocks dictates the need for a new generation of automated and formal system EDA tools and methodologies. High-Level Synthesis (HLS) plays a critical role in the required Electronic System Level (ESL) methodologies. However, most of the available academic and commercial High-Level Synthesis (HLS) tools still do not play an established role in the system and hardware engineering teams. This is true for a number of practical reasons, analyzed and discussed in this work. The present article is a practical perspective of the required fully automated and formal tools, which are needed to constitute integral parts in Electronic Design Automation (EDA) flows. In addition, this article is a useful guide to the system engineer who wants to familiarize with HLS tools and to select the appropriate tool for the everyday engineering practice. The advanced HLS toolset that is analyzed in this paper is developed by the first author, its C-frontend by the second author, and they are both based on formal methods and fully automated techniques, thus they guarantee the correctness of the synthesized hardware implementations. This paper completes with a number of experiments that were executed using the author’s methodology and they are used to evaluate the specific HLS tools. Consequently, a number of conclusions are drawn as well as suggestions for the future directions of HLS technology. In this way, what is practically needed by the hardware systems engineering community is outlined at the end of the paper.

scholarly journals System-level FPGA device driver with high-level synthesis support

2013 ◽  
Author(s):  
Kizheppatt Vipin ◽  
Shanker Shreejith ◽  
Dulitha Gunasekera ◽  
Suhaib A. Fahmy ◽  
Nachiket Kapre
Keyword(s):  
Device Driver ◽  
System Level ◽  
High Level Synthesis ◽  
High Level
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