Abstract
Quantum-dot cellular automata (QCA) technology is considered to be the future of nanoelectronic device fabrication technology. The fabrication density of the transistors in a particular area in the current nanoelectronic industry has saturated. Adroit alternate to current CMOS based VLSI technology is being researched upon. QCA technology is considered to be the noblest post-CMOS era fabrication technology. In this paper, novel energy-efficient QCA designs for 1/2 and 1/3 convolution encoders have been presented. Both the presented designs were proven to be efficient than previously designed circuits. The efficiency of the design is calculated for critical design parameters like cell count, cell area, latency (clock phases), complexity and energy dissipation. The proposed 1/2 convolution encoder uses 21 QCA cells consuming an area of 0.012µm2. The complexity of this design was calculated to be 2. The energy dissipation analysis revealed that the presented circuit dissipated 14.03meV of energy. The proposed 1/3 convolution encoder uses 32 QCA cells consuming an area of 0.025µm2. The energy dissipation analysis revealed that the presented circuit dissipated 16.88meV of energy. Both the proposed designs used only a few more extra cells than the previously designed circuits but induced stronger polarizations and were more fault-tolerant. It was found that the circuits proposed are 25% more energy efficient than previously designed circuits. The latency of the proposed designs was of 2 clock phases, thus making it suitable for high-speed operation. Significant improvement of the designs was done to optimize the circuit for secure nano-communication devices.
<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>
Purpose
This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency.
Design/methodology/approach
The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology.
Findings
QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones.
Originality/value
The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.
Aims:
Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy
efficient embedded system design in post-CMOS technology i.e. QCA.
Objectives:
The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field
programmable gate array architecture (FPGA) with successful simulation based on a next generation technology,
Quantum-dot cellular automata.
Methodology:
Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular
Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency
and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power
dissipation measurement.
Results:
In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in
reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and
multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces
the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and
read latency of proposed CLB is 12 and 7.25 QCA clock respectively.
Conclusion:
The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage
and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the
latency for the proposed CLB in the process.
An Energy Efficient Quantum-dot Cellular Automata Design of 1/2 and 1/3 Convolution Encoder