Computation of Gate-Induced-Drain-Leakage Current Due to Band-to-Band Tunneling for Ultrathin MOSFET

Author(s):  
Krishnendu Roy ◽  
Anal Roy Chowdhury ◽  
Arpan Deyasi
2013 ◽  
Vol 12 (06) ◽  
pp. 1350043 ◽  
Author(s):  
NEELAM SURANA ◽  
BAHNIMAN GHOSH ◽  
BALL MUKUND MANI TRIPATHY ◽  
AKSHAY KUMAR SALIMATH

We propose a Ge / Si graded junctionless transistor (JLT) which helps to reduce the band-to-band tunneling current in off-state for highly doped double gate junctionless transistor (DGJLT). In this paper, we show that there is large band-to-band tunneling (BTBT) current in off-state of silicon-channel and germanium-channel DGJLT, which causes increase in the off-state leakage current by several orders. With the help of band-gap engineering, we found that by using Ge / Si graded channel DGJLT off-state band-to-band tunneling current can be reduced. It is also observed that there is large deviation in the off-state leakage current with variation of drain voltage for Si and Ge body DGJLT, which reduces device stability. It is found that in Ge / Si graded DGJLT variation off-state leakage current with drain voltage is controlled. In Si and Ge , DGJLT electrons from the valence band of the channel tunnel to the conduction band of drain leaves holes which causes increased hole concentration in the channel creating parasitic 'BJT'.


2007 ◽  
Vol 54 (6) ◽  
pp. 2174-2180 ◽  
Author(s):  
Philippe C. Adell ◽  
Hugh J. Barnaby ◽  
Ron D. Schrimpf ◽  
Bert Vermeire

2013 ◽  
Vol 684 ◽  
pp. 295-298
Author(s):  
Seung Min Lee ◽  
Hyun Jun Jang ◽  
Jong Tae Park

A comparative study on off-state breakdown characteristics in nanowire JL and IM multiple gate MOSFETs has been performed for different gate bias voltages and fin widths. In order to understand the drain breakdown mechanism with different transistor structures, the device was simulated using the 3-dimensional ATLAS software. The band-to-band tunneling current and the gate-induced-drain-leakage current trigger the off-state breakdown in JL transistor and IM transistor, respectively. From experiment and simulation, the off-state breakdown voltage is lower in JL transistor than in IM transistor. As the gate is biased more negatively, the off-state breakdown voltages are increased in JL and IM transistors.


1991 ◽  
Vol 12 (3) ◽  
pp. 95-97 ◽  
Author(s):  
T. Ozaki ◽  
A. Nitayama ◽  
T. Hamamoto ◽  
K. Sunouchi ◽  
F. Horiguchi

2021 ◽  
Vol 14 (11) ◽  
pp. 114001
Author(s):  
Tomoyuki Shoji ◽  
Tetsuo Narita ◽  
Yoshitaka Nagasato ◽  
Masakazu Kanechika ◽  
Takeshi Kondo ◽  
...  

Author(s):  
Abdoul Rjoub ◽  
Mamoun Mistarihi ◽  
Nedal Al Taradeh

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper


2006 ◽  
Vol 3 (2) ◽  
pp. 301-311
Author(s):  
Deepanjan Datta

In this paper, we look into the reduction in leakage components of a fully depleted (FD) nanoscale double-gate (DG) MOSFET architecture. Here, we have developed an numerical model for PCHEM-DG MOSFET followed by the gate-controlled band-to-band tunneling leakage and gate leakage currents in the device of 10 nm gate length and observed the reduction in the leakage components over bulk-MOSFETs. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with standard device simulator such as MINIMOS 6.0 for the purpose of validation of the results. A dramatic increase of the gate leakage and Band-to-Band Tunneling (BTBT) leakage in nanoscaled devices drastically increases total leakage power in a logic circuit. This device proposes to reduce this power dissipation. This work provides a simple and intuitive method for lowering of leakage currents which can be very salutary for the future nanoscale device technologies.


Sign in / Sign up

Export Citation Format

Share Document