scholarly journals Accurate leakage current models for MOSFET nanoscale devices

2020 ◽  
Vol 10 (3) ◽  
pp. 2313
Author(s):  
Abdoul Rjoub ◽  
Mamoun Mistarihi ◽  
Nedal Al Taradeh
Keyword(s):  
Leakage Current ◽  
Oxide Thickness ◽  
Nanoscale Devices ◽  
Gate Leakage ◽  
Body Effect ◽  
Accurate Model ◽  
Inversion Channel ◽  
Band To Band Tunneling ◽  
Simulation Results

This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) wasinvestigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Drain PN reverse junction were also modeled witha close and accurate model using a rectangularapproximation method (RJA). The three types of gate leakage (IG) were also modeled and analyzed for parasitic (IGO), inversion channel (IGC), and gate substrate (IGB).In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICEexhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

2011 ◽  
Vol 88 (7) ◽  
pp. 1309-1311 ◽  
Author(s):  
C.H. Fu ◽  
K.S. Chang-Liao ◽  
Y.A. Chang ◽  
Y.Y. Hsu ◽  
T.H. Tzeng ◽  
...  
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Equivalent Oxide Thickness ◽  
Gate Leakage ◽  
High K ◽  
High K Gate Dielectric

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

2003 ◽  
Vol 765 ◽  
Author(s):  
Daewon Ha ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
Katsunori Onishi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Deposition Rate ◽  
Silicon Germanium ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Cmos Process ◽  
Gate Leakage ◽  
Process Technology ◽  
Cmos Scaling

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Study of Leakage Current in Novel Nanoscale Device Architecture depending on Doping Profile

2006 ◽  
Vol 3 (2) ◽  
pp. 301-311
Author(s):  
Deepanjan Datta
Keyword(s):  
Leakage Current ◽  
Doping Profile ◽  
Gate Leakage ◽  
Leakage Currents ◽  
Nanoscale Device ◽  
Fully Depleted ◽  
Dg Mosfet ◽  
Band To Band Tunneling ◽  
Total Leakage ◽  
Intuitive Method

In this paper, we look into the reduction in leakage components of a fully depleted (FD) nanoscale double-gate (DG) MOSFET architecture. Here, we have developed an numerical model for PCHEM-DG MOSFET followed by the gate-controlled band-to-band tunneling leakage and gate leakage currents in the device of 10 nm gate length and observed the reduction in the leakage components over bulk-MOSFETs. Various leakage current components have been discussed and their variations with respect to bias and device parameters are presented. The results have been compared and contrasted with standard device simulator such as MINIMOS 6.0 for the purpose of validation of the results. A dramatic increase of the gate leakage and Band-to-Band Tunneling (BTBT) leakage in nanoscaled devices drastically increases total leakage power in a logic circuit. This device proposes to reduce this power dissipation. This work provides a simple and intuitive method for lowering of leakage currents which can be very salutary for the future nanoscale device technologies.

scholarly journals The Improvement of Reliability of High-k/Metal Gate pMOSFET Device with Various PMA Conditions

2012 ◽  
Vol 2012 ◽  
pp. 1-4
Author(s):  
Yi-Lin Yang ◽  
Wenqi Zhang ◽  
Chi-Yun Cheng ◽  
Wen-kuan Yeh
Keyword(s):  
Leakage Current ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Metal Gate ◽  
Threshold Voltages ◽  
High K ◽  
Nitrogen Annealing

The oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. The threshold voltages of the devices changed with various PMA conditions. The reliability of the devices, especially for the oxygen annealed devices, was improved after PMA treatments.

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