Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

2019 ◽  
Vol 38 (11) ◽  
pp. 5236-5252 ◽  
Author(s):  
Adepu Hariprasad ◽  
Sreenivasa Rao Ijjada
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  

2020 ◽  
Vol 14 (2) ◽  
pp. 1670-1681
Author(s):  
Fouad Ali Yaseen ◽  
Hamed S. Al-Raweshidy

Author(s):  
Esam AlKaldy ◽  
Ali H Majeed ◽  
Mohd Shamian Zainal ◽  
Danial MD Nor

<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>


Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sadat Riyaz ◽  
Vijay Kumar Sharma

Purpose This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency. Design/methodology/approach The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology. Findings QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones. Originality/value The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.


2015 ◽  
Vol 4 (2) ◽  
pp. 190-197 ◽  
Author(s):  
Shadi Sheikhfaal ◽  
Keivan Navi ◽  
Shaahin Angizi ◽  
Ahmad Habibizad Navin

Author(s):  
Emre I. Cosar ◽  
Maurizio Bocca ◽  
Lasse M. Eriksson

Communication between a sink node and a PC can constitute a bottleneck for high data rate applications of wireless sensor networks (WSNs) including, but not limited to, structural health monitoring, condition monitoring, wireless surveillance and patient health monitoring. In this paper, we evaluate four different data acquisition alternatives for data-intensive WSN applications. We will concentrate especially on optimizing UART (universal asynchronous receiver transmitter) communication in conjunction with WSN applications. Furthermore, we propose a new method for sink node to PC communication, which is based on using a USB-connected data acquisition (DAQ) board that samples the node external I/O. This method can provide an efficient solution to transfer data from the sink node to PC at a reasonable cost. Wireless sink node converts the data received from the network into analog signal levels, which are sampled through the DAQ board connected to a PC, and the original data is reconstructed offline. Tests on a wooden bridge built to scale with six wireless sensor nodes and a sink node show that with the proposed method it is possible to collect the data from the network and transfer them onto the PC significantly faster than with the 115.2 kbps UART communication regularly used in WSN applications.


Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1036
Author(s):  
Nuriddin Safoev ◽  
Jun-Cheol Jeon

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.


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