Performance Analysis of III-V and IV Semiconductors Based Double Gate Hetero Material Negative Capacitance TFET

Silicon ◽  
2022 ◽  
Author(s):  
Chithraja Rajan ◽  
Omdarshan Paul ◽  
Dip Prakash Samajdar ◽  
Tarek Hidouri ◽  
Samia Nasr
Keyword(s):  
Performance Analysis ◽  
Negative Capacitance ◽  
Double Gate

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

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