Numerical modeling of radiation-induced charge loss in CMOS floating gate cells

Mediante un modelo numérico desarrollado recientemente y basado en principios físicos, se estudia la respuesta a la radiación de celdas de compuerta flotante programadas/borradas. El rol que juega la captura de carga en los óxidos en el desplazamiento total de la tensión umbral con la dosis es debidamente evaluado a través de la variación de la tasa de captura de los huecos generados por radiación. Se considera un modelo analítico simplificado y se discuten sus limitaciones.

Elucidating the Trajectory of the Charge Transfer Mechanism and Recombination Process of Hybrid Perovskite Solar Cells

Perovskite-based solar cells (PSCs) have attracted attraction in the photovoltaic community since their inception in 2009. To optimize the performance of hybrid perovskite cells, a primary and crucial strategy is to unravel the dominant charge transport mechanisms and interfacial properties of the contact materials. This study focused on the charge transfer process and interfacial recombination within the n–i–p architecture of solar cell devices. The motivation for this paper was to investigate the impacts of recombination mechanisms that exist within the interface in order to quantify their effects on the cell performance and stability. To achieve our objectives, we firstly provided a rationale for the photoluminescence and UV-Vis measurements on perovskite thin film to allow for disentangling of different recombination pathways. Secondly, we used the ideality factor and impedance spectroscopy measurements to investigate the recombination mechanisms in the device. Our findings suggest that charge loss in PSCs is dependent mainly on the configuration of the cells and layer morphology, and hardly on the material preparation of the perovskite itself. This was deduced from individual analyses of the perovskite film and device, which suggest that major recombination most likely occur at the interface.

Charge Sharing and Charge Loss in High-Flux Capable Pixelated CdZnTe Detectors

Cadmium zinc telluride (CdZnTe) detectors are known to suffer from polarization effects under high photon flux due to poor hole transport in the crystal material. This has led to the development of a high-flux capable CdZnTe material (HF-CdZnTe). Detectors with the HF-CdZnTe material have shown promising results at mitigating the onset of the polarization phenomenon, likely linked to improved crystal quality and hole carrier transport. Better hole transport will have an impact on charge collection, particularly in pixelated detector designs and thick sensors (>1 mm). In this paper, the presence of charge sharing and the magnitude of charge loss were calculated for a 2 mm thick pixelated HF-CdZnTe detector with 250 μm pixel pitch and 25 μm pixel gaps, bonded to the STFC HEXITEC ASIC. Results are compared with a CdTe detector as a reference point and supported with simulations from a Monte-Carlo detector model. Charge sharing events showed minimal charge loss in the HF-CdZnTe, resulting in a spectral resolution of 1.63 ± 0.08 keV Full Width at Half Maximum (FWHM) for bipixel charge sharing events at 59.5 keV. Depth of interaction effects were shown to influence charge loss in shared events. The performance is discussed in relation to the improved hole transport of HF-CdZnTe and comparison with simulated results provided evidence of a uniform electric field.

Ag Nanoparticles capped TiO2 Nanowires Array based Capacitive Memory

Glancing angle deposition technique was used to fabricate Ag nanoparticles (NPs) capped TiO2 Nanowire (NW) array structure for capacitive memory application. Electron microscopes confirmed the sandwiched structure of Ag NPs between TiO2 thin-film (TF) and NW. The average length of the vertical TiO2 NW and diameter of Ag NPs (with density ~1012 cm2) were found to be ~ 350 nm ±5 nm and ~3.2 nm ± 0.4 nm, respectively. An enhanced photoluminescence was observed in case of Ag NPs capped TiO2 NWs due to the presence of high carriers as compared to bare TiO2 NW. The capacitance (C) - voltage (V) hysteresis was measured for both Ag NPs capped TiO2 NW and bare TiO2 NW at different sweeping voltage (±3V to ±10 V) at 1 MHz frequency. A high capacitive memory window of 7.12 V was obtained for Ag NP capped TiO2 NW at ±10 V with an excellent endurance upto 1000 cycle. Significantly lesser charge loss of 23% was obtained after a span of 104 s with a hole and electron loss of 10.6% and 17.8% respectively. The program and erase process in the device was explained with the help of a band diagram.

Cell Charge Loss by Formation of Inversion Channel in DRAM

As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

Reliability prediction for Flash memories Retention failure by charge loss

<p>This article represents a new method for Data Retention failure (DR) in NAND Flash memories by analyzing the <b>charge leakage</b> phenomena. Retention failure accrue when stored data changes its level. This usually happens at and because of a high temperature environment that accelerate leakage.</p> <p>The amount of electron charge in the cell is rather hard to calculate. However, we know that a verification process done at the end of the programming with respect to the amount of charge, is apparently enough to indicate the proper logical level. Moreover, when the cell is exposed to high temperature the charge leaks out but the manufacturer`s guarantee that the memory storage will withstand the JEDS218 standard, this mean that this amount of charge should be enough for 10 years at temperature ambient range of 25÷55°C. Hence, after 10 years, in the worst-case scenario, the amount of charge might be so low that its results can adversely affect its logical level.</p> <p>In our previous work, we found that the programed cell array affected by temperature as shown in figure 1, begin with the average voltage is equal to V_t1 and later, when the leakage occurs, the average voltage decreases while the variation increases.</p>