Background:
This paper presents the comparative study of power dissipation, delay and
power delay product (PDP) of different full adders and multiplier designs.
Methods:
Full adder is the fundamental operation for any processors, DSP architectures and VLSI
systems. Here ten different full adder structures were analyzed for their best performance using a
Mentor Graphics tool with 180nm technology.
Results:
From the analysis result high performance full adder is extracted for further higher level
designs. 8T full adder exhibits high speed, low power delay and low power delay product and
hence it is considered to construct four different multiplier designs, such as Array multiplier,
Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures
of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a
constant W/L aspect ratio.
Conclusion:
From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier
but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but
exhibits more time delay and low PDP.
A CNFET full adder cell design for high-speed arithmetic units
