scholarly journals Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography

2019 ◽  
Vol 3 (4) ◽  
pp. 382-396 ◽  
Author(s):  
Ioannis Karageorgos ◽  
Mehmet M. Isgenc ◽  
Samuel Pagliarini ◽  
Larry Pileggi
Keyword(s):  
Integrated Circuit ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Public Key Cryptography ◽  
Cmos Technology ◽  
Performance Level ◽  
The Other ◽  
Public Key ◽  
Critical Systems ◽  
Software Vulnerabilities

AbstractIn today’s globalized integrated circuit (IC) ecosystem, untrusted foundries are often procured to build critical systems since they offer state-of-the-art silicon with the best performance available. On the other hand, ICs that originate from trusted fabrication cannot match the same performance level since trusted fabrication is often available on legacy nodes. Split-Chip is a dual-IC approach that leverages the performance of an untrusted IC and combines it with the guaranties of a trusted IC. In this paper, we provide a framework for chip-to-chip authentication that can further improve a Split-Chip system by protecting it from attacks that are unique to Split-Chip. A hardware implementation that utilizes an SRAM-based PUF as an identifier and public key cryptography for handshake is discussed. Circuit characteristics are provided, where the trusted IC is designed in a 28-nm CMOS technology and the untrusted IC is designed in an also commercial 16-nm CMOS technology. Most importantly, our solution does not require a processor for performing any of the handshake or cryptography tasks, thus being not susceptible to software vulnerabilities and exploits.

scholarly journals Revisiting Sum of Residues Modular Multiplication

2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Yinan Kong ◽  
Braden Phillips
Keyword(s):  
Public Key Cryptography ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Public Key ◽  
Modular Multiplication ◽  
Residue Number ◽  
The Cost

In the 1980s, when the introduction of public key cryptography spurred interest in modular multiplication, many implementations performed modular multiplication using a sum of residues. As the field matured, sum of residues modular multiplication lost favor to the extent that all recent surveys have either overlooked it or incorporated it within a larger class of reduction algorithms. In this paper, we present a new taxonomy of modular multiplication algorithms. We include sum of residues as one of four classes and argue why it should be considered different to the other, now more common, algorithms. We then apply techniques developed for other algorithms to reinvigorate sum of residues modular multiplication. We compare FPGA implementations of modular multiplication up to 24 bits wide. The sum of residues multipliers demonstrate reduced latency at nearly 50% compared to Montgomery architectures at the cost of nearly doubled circuit area. The new multipliers are useful for systems based on the Residue Number System (RNS).

A Security of Circular Email in Manufacturing

2015 ◽  
Vol 752-753 ◽  
pp. 1296-1300
Author(s):  
Puchong Subpratatsavee ◽  
Chanchira Chintho ◽  
Suchai Tanaiadehawoot
Keyword(s):  
Public Key Cryptography ◽  
The Other ◽  
Public Key ◽  
External Relations ◽  
Email Address ◽  
Manufacturing Organizations ◽  
Applied Technology ◽  
Paper Form ◽  
Media Message

In present, manufacturing organizations in some countries will have to submitinformation to both internal and external to the organization, called circular mail to report newswithin the organization or external relations. Administrative officer is responsibility about to senda circular mail for each organization and will be responsible for receiving letters in paper form orpublication or media message. Then the administrative officer will be read and extracted the letterand send a message in the form of emails to receivers as indicated on the letter. In mailings sendsuch potential attacks from disgruntled individuals; such as a change of email messages duringtransmission or identity thieves use a fake email address to send officials to the other party. If anattack occurs, the organization will make a loss. In terms of stability credibility and security in theuse of corporate email. This paper presents a model and how to send an email or letter online ina format that is more stable and secure by the applied technology of public key cryptography andhash function to encrypt the message to provide stability and security in the mail's circulars online.

scholarly journals Optimizing the Decoding Process of a Post-Quantum Cryptographic Algorithm

2017 ◽  
Author(s):  
Antonio Guimarães ◽  
Diego F. Aranha ◽  
Edson Borin
Keyword(s):  
State Of The Art ◽  
Public Key Cryptography ◽  
Public Key ◽  
Constant Time ◽  
Side Channel ◽  
Security Level ◽  
Encryption Scheme ◽  
Cryptographic Algorithm ◽  
Overall Performance ◽  
Quantum Public Key

QcBits is a state-of-the-art constant-time implementation of a code-based encryption scheme for post-quantum public key cryptography. This paper presents an optimized version of its decoding process, which is used for message decryption. Our implementation leverages SSE and AVX instructions extensions and performs 3.6 to 4.8 times faster than the original version, while preserving the 80-bit security level and constant time execution. We also provide experimental data that indicates a further 1.4-factor speedup supposing the existence of instructions for vectorial conditional moves and 256-bit register shifts. Finally, we implemented countermeasures for side-channel security and showed that they do not affect the overall performance.

scholarly journals Development of a Secured Shared Processing System

10.28945/2156 ◽  
2015 ◽  
Author(s):  
Aderonke Peace Akinduro ◽  
Boniface Kayode Alese ◽  
Olufunso Dayo Alowolodu ◽  
Aderonke Favour-Bethy Thompson ◽  
Akintoba Emmanuel Akinwonmi
Keyword(s):  
Operating System ◽  
Computer System ◽  
Distributed System ◽  
Communication Channel ◽  
Processing System ◽  
Public Key Cryptography ◽  
The Other ◽  
Public Key

The most common way of ensuring confidentiality of data or documents by individuals, governments, and institutions such as banks, hospitals, and other commercial enterprises is by consigning their secrets to a computer system. But this has not solved the problems of upholding security, instead they are more compounded due to the fact that secrets sharing is generally desired but only in a tightly controlled manner. This could be resolved by the introduction of a secured shared processing system. Secured shared processing system is a system that comprises of several computers whereby one stands as a secured, trusted system while the other systems are connected to it. The system do not divide up a memory or a clock; the computers only communicate with each other by exchanging messages over a communication channel; and each computer has its own memory and operates on its own operating system. This is achieved with the aid of Cryptographic mechanisms in which EI Gamal model was adopted as a Public-key cryptography scheme which will be applied on a workstation distributed System.

scholarly journals Multiplicative Masking for AES in Hardware

2018 ◽  
pp. 431-468
Author(s):  
Lauren De Meyer ◽  
Oscar Reparaz ◽  
Begül Bilgin
Keyword(s):  
Design Process ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Second Order ◽  
The Other ◽  
Bivariate Analysis ◽  
Side Channel ◽  
Power Model ◽  
First Order ◽  
Previous State

Hardware masked AES designs usually rely on Boolean masking and perform the computation of the S-box using the tower-field decomposition. On the other hand, splitting sensitive variables in a multiplicative way is more amenable for the computation of the AES S-box, as noted by Akkar and Giraud. However, multiplicative masking needs to be implemented carefully not to be vulnerable to first-order DPA with a zero-value power model. Up to now, sound higher-order multiplicative masking schemes have been implemented only in software. In this work, we demonstrate the first hardware implementation of AES using multiplicative masks. The method is tailored to be secure even if the underlying gates are not ideal and glitches occur in the circuit. We detail the design process of first- and second-order secure AES-128 cores, which result in the smallest die area to date among previous state-of-the-art masked AES implementations with comparable randomness cost and latency. The first- and second-order masked implementations improve resp. 29% and 18% over these designs. We deploy our construction on a Spartan-6 FPGA and perform a side-channel evaluation. No leakage is detected with up to 50 million traces for both our first- and second-order implementation. For the latter, this holds both for univariate and bivariate analysis.

Efficient modular exponential algorithms compatible with hardware implementation of public-key cryptography

2016 ◽  
Vol 9 (16) ◽  
pp. 3105-3115 ◽  
Author(s):  
Satyanarayana Vollala ◽  
Krishnan Geetha ◽  
Natarajan Ramasubramanian
Keyword(s):  
Hardware Implementation ◽  
Public Key Cryptography ◽  
Public Key
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