Laser-induced front side etching of fused silica with XeF excimer laser using thin metal layers

2012 ◽  
Vol 258 (23) ◽  
pp. 9138-9142 ◽  
Author(s):  
Pierre Lorenz ◽  
Martin Ehrhardt ◽  
Anja Wehrmann ◽  
Klaus Zimmer
2012 ◽  
Vol 209 (6) ◽  
pp. 1114-1118 ◽  
Author(s):  
Pierre Lorenz ◽  
Martin Ehrhardt ◽  
Klaus Zimmer

RSC Advances ◽  
2014 ◽  
Vol 4 (89) ◽  
pp. 48135-48143 ◽  
Author(s):  
Michael Kracker ◽  
Wolfgang Wisniewski ◽  
Christian Rüssel

This article shows that multiple crystallographic textures coexist in thermally dewetted metal nano particles in contrast to the usually assumed or presented 111 texture.


Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.


Author(s):  
Fei Long Xu ◽  
Phoumra Tan ◽  
Dan Nuez

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.


2013 ◽  
Vol 40 (4) ◽  
pp. 0402008
Author(s):  
单耀莹 Shan Yaoying ◽  
赵江山 Zhao Jiangshan ◽  
李慧 Li Hui ◽  
王倩 Wang Qian ◽  
沙鹏飞 Sha Pengfei ◽  
...  

1988 ◽  
Vol 27 (15) ◽  
pp. 3124 ◽  
Author(s):  
Rod S. Taylor ◽  
Kurt E. Leopold ◽  
Robert K. Brimacombe ◽  
Stephen Mihailov

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