A Novel Deprocessing Technique for Revealing Transistor-Level Damage on 7nm FinFET Devices

2020 ◽  
Author(s):  
Fei Long Xu ◽  
Phoumra Tan ◽  
Dan Nuez
Keyword(s):  
High Resolution ◽  
Flip Chip ◽  
Fault Localization ◽  
Wet Etching ◽  
Efficient Technique ◽  
Solid Immersion Lens ◽  
Front Side ◽  
Flip Chip Packaging ◽  
Metal Layers

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

Simple and Effective Technique of Backside Deprocessing of Thin Flip Chip Package

2013 ◽  
Author(s):  
Suk Ho Lee ◽  
Chan Hee Park ◽  
Seung Joon Cha ◽  
Eun Cheol Lee ◽  
Kyu Shik Hong
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Processing Technique ◽  
Wet Etching ◽  
Bulk Silicon ◽  
Front Side ◽  
Mechanical Grinding ◽  
Effective Technique ◽  
Processing Procedure ◽  
Silicon Thickness

Abstract This paper introduces a simple and effective technique of backside de-processing procedure. This technique reduces time and steps by simple wet etching. The front-side deprocessing requires many steps, such as wet and dry etching and parallel lapping, and also backside de-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing with TMAH and KOH which commonly have been used for bulk silicon etchant. The results show uniform backside images without any damage or residue. This backside de-processing technique was applied in two case studies to facilitate failure analysis.

FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Effects of Backside Circuit Edit on Transistor Characteristics

2007 ◽  
Author(s):  
R.K. Jain ◽  
T. Malik ◽  
T.R. Lundquist ◽  
Q.S. Wang ◽  
R. Schlangen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Intrinsic Parameters ◽  
Chip Type ◽  
Device Structures ◽  
Before And After ◽  
Silicon Device ◽  
Metal Layers

Abstract Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Failure Analysis of Short Faults on Advanced Wire-Bond and Flip-Chip Packages with Scanning SQUID Microscopy

2004 ◽  
Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad
Keyword(s):  
Magnetic Fields ◽  
Integrated Circuits ◽  
Quantum Interference ◽  
Flip Chip ◽  
Infrared Emission ◽  
Fault Analysis ◽  
Wire Bond ◽  
Overlay Design ◽  
Scanning Squid ◽  
Metal Layers

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

2014 ◽  
Vol 62 (10) ◽  
pp. 2337-2356 ◽  
Author(s):  
Bon-Hyun Ku ◽  
Ozgur Inac ◽  
Michael Chang ◽  
Hyun-Ho Yang ◽  
Gabriel M. Rebeiz
Keyword(s):  
Flip Chip ◽  
Phased Array ◽  
High Isolation ◽  
High Linearity ◽  
Flip Chip Packaging
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