Electrical transport properties of graphene-covered-Cu wires grown by chemical vapor deposition

2012 ◽  
Vol 12 (1) ◽  
pp. 115-118 ◽  
Author(s):  
Kwonjae Yoo ◽  
E.K. Seo ◽  
S.J. Kim ◽  
W. Kim ◽  
M.G. Park ◽  
...  
Nanoscale ◽  
2014 ◽  
Vol 6 (21) ◽  
pp. 12943-12951 ◽  
Author(s):  
Dongmok Lee ◽  
Gi Duk Kwon ◽  
Jung Ho Kim ◽  
Eric Moyen ◽  
Young Hee Lee ◽  
...  

Graphene resistivity decreases as the surface roughness of the copper foils decreases. Small grain polycrystalline graphene films grown on pre-annealed and electropolished copper exhibit a sheet resistance of 210 Ω □−1.


2002 ◽  
Vol 80 (19) ◽  
pp. 3548-3550 ◽  
Author(s):  
Jae-Ryoung Kim ◽  
Hye Mi So ◽  
Jong Wan Park ◽  
Ju-Jin Kim ◽  
Jinhee Kim ◽  
...  

2004 ◽  
Vol 96 (12) ◽  
pp. 7306-7311 ◽  
Author(s):  
Nicola Pinto ◽  
Marco Ficcadenti ◽  
Lorenzo Morresi ◽  
Roberto Murri ◽  
Giuseppina Ambrosone ◽  
...  

Author(s):  
Yunyu Wang ◽  
Zhen Yao ◽  
Shi Li ◽  
Paul S. Ho

As devices continue to scale down to the 50 nm technology node, current Cu/low k interconnect technology will face a number of challenges including reduced current carrying capabilities, decreased thermal conductivity, and reliability problems due to electromigration at large current densities. Carbon nanotubes (CNTs) with their unique structural, thermal and electrical transport properties have been suggested as a promising candidate as interconnect structures for future microelectronics. In this study we have demonstrated the growth of vertically aligned, highly dense CNT arrays by thermal chemical vapor deposition (CVD). It was found that a thin layer of tantalum (Ta), which was originally used as the barrier layer in copper interconnects, may enhance a uniform growth and better vertical alignments of CNT arrays. We have also developed a nanofabrication process of the first-level CNT via structures.


1982 ◽  
Vol 18 ◽  
Author(s):  
F. A. Ponce ◽  
W. Stutius ◽  
J. G. Werthen

The lattice structure of ZnSe grown on GaAs by a low temperature low pressure organometallic chemical vapor deposition (CVD) process was studied using high resolution transmission electron microscopy. The defect structure of ZnSe epitaxial layers and of their interface with the GaAs substrate was directly imaged in cross section for GaAs substrate surfaces in the <100> and <111> orientations. It is shown that the ZnSe layers grow indeed epitaxially. The ZnSe layers grown on GaAs(100) contain a large density of faulted loops which are extrinsic in nature, whereas the prevailing defects in ZnSe layers grown on GaAs(111)B substrates are microtwins and stacking faults parallel to the filmsubstrate interface. A possible connection between the observed defect structure and the reported photoluminescence and electrical transport properties of ZnSe layers grown by organometallic CVD is also discussed.


2019 ◽  
Vol 5 (2) ◽  
pp. eaau3407 ◽  
Author(s):  
H. Nakajima ◽  
T. Morimoto ◽  
Y. Okigawa ◽  
T. Yamada ◽  
Y. Ikuta ◽  
...  

The distribution of defects and dislocations in graphene layers has become a very important concern with regard to the electrical and electronic transport properties of device applications. Although several experiments have shown the influence of defects on the electrical properties of graphene, these studies were limited to measuring microscopic areas because of their long measurement times. Here, we successfully imaged various local defects in a large area of chemical vapor deposition graphene within a reasonable amount of time by using lock-in thermography (LIT). The differences in electrical resistance caused by the micrometer-scale defects, such as cracks and wrinkles, and atomic-scale domain boundaries were apparent as nonuniform Joule heating on polycrystalline and epitaxially grown graphene. The present results indicate that LIT can serve as a fast and effective method of evaluating the quality and uniformity of large graphene films for device applications.


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