UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

2009 ◽  
Vol 86 (4-6) ◽  
pp. 636-638 ◽  
Author(s):  
H. Schmitt ◽  
B. Amon ◽  
S. Beuer ◽  
S. Petersen ◽  
M. Rommel ◽  
...  
2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000398-000424
Author(s):  
Doug Shelton ◽  
Tomii Kume

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000790-000793 ◽  
Author(s):  
Doug Shelton ◽  
Tomii Kume

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.


2005 ◽  
Vol 82 (2) ◽  
pp. 180-188 ◽  
Author(s):  
Jun-ho Jeong ◽  
Ki-don Kim ◽  
Young-suk Sim ◽  
Hyonkee Sohn ◽  
Eung-sug Lee

ACS Photonics ◽  
2021 ◽  
Author(s):  
Vincent J. Einck ◽  
Mahsa Torfeh ◽  
Andrew McClung ◽  
Dae Eon Jung ◽  
Mahdad Mansouree ◽  
...  

Nanomaterials ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 710
Author(s):  
Andre Mayer ◽  
Hella-Christin Scheer

When nanoimprint serves as a lithography process, it is most attractive for the ability to overcome the typical residual layer remaining without the need for etching. Then, ‘partial cavity filling’ is an efficient strategy to provide a negligible residual layer. However, this strategy requires an adequate choice of the initial layer thickness to work without defects. To promote the application of this strategy we provide a ‘guiding chart’ for initial layer choice. Due to volume conservation of the imprint polymer this guiding chart has to consider the geometric parameters of the stamp, where the polymer fills the cavities only up to a certain height, building a meniscus at its top. Furthermore, defects that may develop during the imprint due to some instability of the polymer within the cavity have to be avoided; with nanoimprint, the main instabilities are caused by van der Waals forces, temperature gradients, and electrostatic fields. Moreover, practical aspects such as a minimum polymer height required for a subsequent etching of the substrate come into play. With periodic stamp structures the guiding chart provided will indicate a window for defect-free processing considering all these limitations. As some of the relevant factors are system-specific, the user has to construct his own guiding chart in praxis, tailor-made to his particular imprint situation. To facilitate this task, all theoretical results required are presented in a graphical form, so that the quantities required can simply be read from these graphs. By means of examples, the implications of the guiding chart with respect to the choice of the initial layer are discussed with typical imprint scenarios, nanoimprint at room temperature, at elevated temperature, and under electrostatic forces. With periodic structures, the guiding chart represents a powerful and straightforward tool to avoid defects in praxis, without in-depth knowledge of the underlying physics.


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