Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

2013 ◽  
Vol 53 (12) ◽  
pp. 1857-1862 ◽  
Author(s):  
R. Foissac ◽  
S. Blonkowski ◽  
M. Kogelschatz ◽  
P. Delcroix ◽  
M. Gros-Jean ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
Gate Stack ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
High K

Nanoscale Observations for Degradation Phenomena in SiO2 and High－k Gate lnsulators Using Conductive－Atomic Force Microscopy

2005 ◽  
Author(s):  
Shigeaki Zaima ◽  
Akiyoshi Seko ◽  
Yukihiko Watanabe ◽  
Toshifumi Sago ◽  
Mitsuo Sakashita ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
High K

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

2003 ◽  
Author(s):  
Jon C. Lee ◽  
J. H. Chuang
Keyword(s):  
Atomic Force Microscopy ◽  
Integrated Circuits ◽  
Fault Localization ◽  
Electrical Characterization ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Optical Electron ◽  
Defect Isolation ◽  
Voltage Contrast

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

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