Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Experimental Evaluation ◽  
Flip Chip ◽  
Solder Joint Reliability ◽  
Snagcu Solder ◽  
Joint Reliability

Evaluation of solder joint reliability in flip chip package under thermal shock test

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung
Keyword(s):  
Solder Joint ◽  
Thermal Shock ◽  
Flip Chip ◽  
Thermal Shock Test ◽  
Solder Joint Reliability ◽  
Shock Test ◽  
Joint Reliability

FCBGA Footprints and Solder Joint Reliability

2004 ◽  
Author(s):  
Frank Z. Liang ◽  
Rick L. Williams
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Electrical Performance ◽  
Solder Joint Reliability ◽  
Routing Optimization ◽  
Joint Reliability ◽  
Cost Constraints ◽  
Package Size ◽  
Empirical Tests ◽  
The One

As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer’s critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models.

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